RISC-V: Hypervisor extension - Incorrect handling of mip register

Host environment

• Operating system: Ubuntu 22.04.5 LTS
• OS/kernel version: 6.8.0-79-generic
• Architecture: x86
• QEMU flavor: qemu-system-riscv64
• QEMU version: 10.1.0 (commit f8b2f64e)
• QEMU command line:

  ./qemu-system-riscv64
       -nographic \
       -machine virt \
       -cpu rv64,g=on,c=on,h=on\
       -m 512M \
       -bios none \
       -kernel "build/qemu/rvh_test.bin" 

Emulated/Virtualized environment

• Operating system: - (baremetal)
• OS/kernel version: - (baremetal)
• Architecture: RISC-V (riscv64-softmmu)

Description of problem

I am executing tests for the riscv hypervisor extension from https://github.com/josecm/riscv-hyp-tests. In particular, test mip(2) in the check_xip_regs category fails. Following is the analysis of what the test is checking, what the test expects and what QEMU does.

What the test checks The test checks the value of the hvip register that a hypervisor can write to indicate virtual interrupts intended for VS-mode. For this, the test sets all bits in the hvip register to mark all possible interrupts that can be intended for VS mode. Finally, the test reads the mip register.

What the test expects The test expects that bits VSEIP (bit 10), VSTIP (bits 6) and VSSIP (bits 2) in mip are the only ones set.

What qemu does Qemu also sets bit 13.

Comments Following the specification, bit 13 should not be set.

Steps to reproduce

Assuming a riscv64-unknown-elf- cross compiler is installed in the machine:

1. git clone https://github.com/josecm/riscv-hyp-tests.git
2. cd riscv-hyp-tests
3. LOG_LEVEL=LOG_VERBOSE PLAT=qemu make
4. Execute the previous command line.

Additional information

Example output:

...
VERBOSE: setting all in hvip
...
        mip                                                                                 FAILED
        (               - 0000000000002444 0000000000000444)
...