ARM register DBGDTR_EL0 incorrectly causes undefined exception

The debug communication channel is not implemented by QEMU, and the related system registers are generally implemented as constant RAZ/WI registers. However, the handling of the DBGDTR_EL0 register is not quite correct. Attempting to read or write this register generates an UNDEFINED exception instead of the expected RAZ/WI behavior.

The following code gives a register definition that is named DBGDTR_EL0, but actually handles the related (but distinct) registers DBGDTRRX_EL0 and DBGDTRTX_EL0. These registers share the op code encoding op0 = 2, op1 = 3, CRn = 0, CRm = 5, op2 = 0, but DBGDTR_EL0 has the encoding op0 = 2, op1 = 3, CRn = 0, CRm = 4, op2 = 0 (CF ARM DDI 0487K.a, sections D23.3.6, D23.3.7 and D23.3.8).

https://gitlab.com/qemu-project/qemu/-/blob/master/target/arm/debug_helper.c?ref_type=heads#L991-995