aarch64 register MDCCINT_EL1 exhibits bizzare behavior

A small collection of system registers (MDCCINT_EL1, DBGVCR and DBGVCR32_EL2) are implemented with type ARM_CP_NOP (See: https://gitlab.com/qemu-project/qemu/-/blob/master/target/arm/debug_helper.c?ref_type=heads#L1032-1048). As a result mrs and msr instructions targeting these registers are ignored. The practical effect of this is that reading one of these registers appears to produce "garbage" values, as the temporary register target of the read simply retains whatever stale value it had before. One does not generally expect a register to behave like this, and I only discovered this fun fact after a very confusing day of debugging some context-switching code. IMO, this behavior is clearly a bug, even if it was intended originally (https://lists.nongnu.org/archive/html/qemu-devel/2016-10/msg01174.html).

I haven't extracted a minimal reproducer, but it's easy to observe on any reasonably recent qemu-system-aarch64. Just execute some snippet like:

mrs x9 MDCCINT_EL1

And observe that x9 retains whatever value it had before.

Ideally, these registers should have storage backing them and return values written there, even if the associated features are not fully implemented. In lieu of that, read-as-zero/write-ignore behavior would at least be sensible.