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This bug has been copied automatically from: https://bugs.launchpad.net/qemu/+bug/1843795
Reported by 'Paul Clarke' on 2019-09-12 :

Using mtfsf instruction can clear the FPSCR FI bit incorrectly.  This code
snippet exhibits the issue:
--
  fpscr.ll = 0x1fffffff;
  __builtin_mtfsf (0b11111111, fpscr.d);
  fpscr.d = __builtin_mffs ();
--

On POWER9 hardware:
mffs    : FPSCR = 0x000000007ffff7ff

On qemu (git master; "-cpu POWER9"):
--
$ ./mtfsf
mffs    : FPSCR = 0x000000007ffdffff
--

Two differences:
bit 52: "reserved", so maybe a "don't care" case
bit 46: "FI"

$ git log -1 master
commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1
Merge: 019217c 2531164
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Mon Sep 9 09:48:34 2019 +0100

I tracked the clear is coming from do_float_check_status, likely the one
in gen_mtfsf, but then I get lost figuring out what _should_ be happening.
:-/

Test attached.