MIPS MT dvpe does not regard VPEConf0.MVP

This bug has been copied automatically from: https://bugs.launchpad.net/qemu/+bug/1926277
Reported by 'Hansni Bu' on 2021-04-27 :

Hi,

According to MIPS32® Architecture for Programmers VolumeIV-f: The MIPS® MT
Application-Specific Extension to the MIPS32® Architecture, for
instruction: dvpe, evpe:

If the VPE executing the instruction is not a Master VPE, with the MVP bit
of the VPEConf0 register set, the EVP bit is unchanged by the instruction.

The pseudo code is:

data ←  MVPControl
GPR[rt] ←  data
if(VPEConf0.MVP = 1) then
  MVPControl.EVP ←  sc
endif

However the helper functions of dvpe, evpe does not regard the
VPEConf0.MVP bit, namely, it does not check if the VPE is a master VPE.
Code is copied below as:

target_ulong helper_dvpe(CPUMIPSState *env)
{
    CPUState *other_cs = first_cpu;
    target_ulong prev = env->mvp->CP0_MVPControl;

    CPU_FOREACH(other_cs) {
        MIPSCPU *other_cpu = MIPS_CPU(other_cs);
        /* Turn off all VPEs except the one executing the dvpe.  */
        if (&other_cpu->env != env) {
            other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
            mips_vpe_sleep(other_cpu);
        }
    }
    return prev;
}

Is this a bug?

QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked.