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sifive_e : erroneous CLINT frequency

Host environment

  • Operating system: MacOS Sonoma
  • OS/kernel version: Darwin Kernel Version 23.0.0: Fri Sep 15 14:43:05 PDT 2023; root:xnu-10002.1.13~1/RELEASE_ARM64_T6020 arm64
  • Architecture: Arm
  • QEMU flavor: qemu-system-riscv32
  • QEMU version: QEMU emulator version 8.1.2
  • QEMU command line: 
    ./qemu-system-riscv32 -machine sifive_e,revb=true -nographic -kernel bare_metal_app_using_clint

Emulated/Virtualized environment

  • Operating system: Bare metal
  • OS/kernel version: Precompiled Rust executable
  • Architecture: RISCV32

Description of problem

CLINT's mtime updates at a clock frequency of 10 MHz, whereas SiFive documentation shows that its clock frequency is 32.768 kHz (i.e., the RTC clock).

This difference leads to unexpected timing behavior. Due to the difference, it can even trigger multiple nested interrupts as the IRQ routine is not able to return before a new timer interrupt is triggered.

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