QEMU gives wrong MPIDR value for Arm CPU types with MT=1

Some Arm cores advertise themselves as SMT, by setting the MT bit in the MPIDR and putting the CPU number in the Aff1 field, unlike traditional single-thread cores where MT is 0 and the CPU number is in Aff0. QEMU's implementation of MPIDR (in mpidr_read_val()) always reports an MT=0 style MPIDR, which means we're reporting the wrong value for these CPU types:

• Cortex-A55
• Cortex-A76
• Neoverse-N1 (list correct as of April 2023).

We should ideally report the same kind of MPIDR that the hardware does. I think I would implement this by adding a bool ARMCPU::cpuid_in_aff1 similar to the existing ARMCPU::mp_is_up, and making mpidr_read_val() act appropriately.

There is some awkwardness with migration compat -- we would need to have a CPU property to suppress this change that we can then set in the hw_compat_8_1 array so that guests on older versioned machine types don't see a sudden change in the MPIDR value if they're migrated to the new QEMU.

See also this mailing list thread from last year: https://lore.kernel.org/qemu-devel/CAFEAcA9P2-v94p8H8+ktnf-Yf-rucbGySXE6AGPdwvDxXfP=ZA@mail.gmail.com/