Tricore: different definitions of pcxi register field

When I was using qemu to execute tricore firmware, there were frequent crashes when doing context switches. I found that QEMU's definition for pcxi register fields is different from the manual. QEMU：

// qemu/target/tricore/cpu.h
#define MASK_PCXI_PCPN 0xff000000
#define MASK_PCXI_PIE_1_3  0x00800000
#define MASK_PCXI_PIE_1_6  0x00200000
#define MASK_PCXI_UL   0x00400000  
#define MASK_PCXI_PCXS 0x000f0000
#define MASK_PCXI_PCXO 0x0000ffff

In the manual (https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd, Page 36)

We can find that the location of pxci.ul is different. When creating a task, Tricore needs to construct a PCXI register to prepare for subsequent function calls, but due to the different uses of pcxi.ul, when the function returns, the mismatch of the context flag pcxi.ul will cause an error trap.