aspeed: Fix first byte in I2C old register mode slave receive
Found a bug (and proposed a fix, and got a review) in the newly added Aspeed I2C slave mode functionality:
https://lore.kernel.org/qemu-devel/20220820225712.713209-1-peter@pjd.dev/#t
This is not a regression in QEMU, just a bug in the new feature.
Emulated/Virtualized environment
- Operating system: Linux
- OS/kernel version: Linux 5.15
- Architecture: arm
Description of problem
The first byte of data received through the Aspeed I2C slave controller through the old-register mode (specifically byte-buffered, not pool buffered or DMA buffered) is incorrect. It should be the 8-bit I2C slave address for the transfer, which will be the 7-bit I2C slave address of the I2C controller shifted left 1, and 1 or 0 for the lowest bit (is-slave-to-master-transfer, or is-master-to-slave-transfer).
Steps to reproduce
You could use the simulated I2C slave EEPROM https://docs.kernel.org/i2c/slave-eeprom-backend.html, but you need another I2C model to send data to it.
Alternatively, you can take this downstream patch and run the qtest in it. It has a test case for slave-mode rx in old-register mode:
Additional information
I already created the fix, it's pretty simple, I submitted it to the mailing list and Klaus (the author of that section of the Aspeed I2C controller) reviewed it. https://lore.kernel.org/qemu-devel/20220820225712.713209-1-peter@pjd.dev/#t
This is relatively critical fix, but since slave-mode I2C is not widely used at this point, it's probably fine to ship with this bug. My team uses the master branch for everything anyways.