AArch64: SCR_EL3.RW behaves incorrectly for CPUs with no AArch32

Host environment

• Operating system: Any
• OS/kernel version: Any
• Architecture: Any
• QEMU flavor: qemu-system-aarch64
• QEMU version: QEMU emulator version 7.0.0 (v6.2.0-3146-g7e0e865ad5-dirty)

Emulated/Virtualized environment

• Architecture: ARM

Description of problem

In the ARM DDI 0487G.a, D13-3572, the SCR_EL3.RW bit is defined as RAO/WI if both EL2 and EL1 don't support Aarch32. However, the function scr_write in target/arm/helper.c does not reflect this behavior, even though it checks for Aarch32 EL1 support.

This would break this EL3 code, which should run on cpu reset to attempt to return to EL1:

mov x1, #((1<<0)|(1<<2)|(1<<6)|(1<<7)|(1<<8)|(1<<9)) ; EL1h, DAIF masked
mov SPSR_EL3, x1
adr x1, 1f
msr ELR_EL3, x1
eret
1:
; something something

Additional information