Samsung Galaxy Trend Plus (samsung-kylepro): Mainlining attempt
Motivation
I opened this issue to document my mainlining progress and to share my findings.
This device uses the BCM21664T SoC which already has some support in mainline. It also uses the same VideoCore IV as the Raspberry Pi's which may help in getting hardware acceleration working later down the line.
I followed the mainlining guide.
Current status
After following the guide and making some trivial tweaks to the DTS, I got serial output
The current roadblock is figuring out why the periperal clocks aren't getting enabled.
[ 0.000000][ T0] __ccu_wait_bit: master_ccu/0x0358 bit 18 was never set
[ 0.000000][ T0] __peri_clk_init: error initializing gate for sdio1
[ 0.000000][ T0] __ccu_wait_bit: master_ccu/0x0364 bit 18 was never set
...
[ 0.000000][ T0] Broadcom master_ccu initialization had errors
In order to get anything else working these clocks need to work. Interestingly the clock for the internal eMMC is working. So i am able to detect that partition. My theory is that the bootloader has already initialized the clock for the internal storage.
The SoC apparently uses "Kona style CCU's" (Clock Control Units, I think) that controls the clocks. I've narrowed down the problem to the gating status bit in the clock control registers. I have no idea why the gates aren't getting enabled. The addresses and offsets are the same as downstream.
Help and ideas are welcome! :D