• Takeshi Kihara's avatar
    pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering · 5219aa33
    Takeshi Kihara authored
    MOD_SEL register bit numbering was different from R-Car D3 SoC and
    R-Car H3/M3-[WN] SoCs.
    
    MOD_SEL 1-bit      H3/M3-[WN]  D3
    ===============    ==========  =====
    Set Value = H'0    b'0         b'0
    Set Value = H'1    b'1         b'1
    
    MOD_SEL 2-bits     H3/M3-[WN]  D3
    ===============    ==========  =====
    Set Value = H'0    b'00        b'00
    Set Value = H'1    b'01        b'10
    Set Value = H'2    b'10        b'01
    Set Value = H'3    b'11        b'11
    
    MOD_SEL 3-bits     H3/M3-[WN]  D3
    ===============    ==========  =====
    Set Value = H'0    b'000       b'000
    Set Value = H'1    b'001       b'100
    Set Value = H'2    b'010       b'010
    Set Value = H'3    b'011       b'110
    Set Value = H'4    b'100       b'001
    Set Value = H'5    b'101       b'101
    Set Value = H'6    b'110       b'011
    Set Value = H'7    b'111       b'111
    
    This patch replaces the #define name and value of MOD_SEL.
    Signed-off-by: 's avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
    Fixes: 794a6711 ("pinctrl: sh-pfc: Initial R8A77995 PFC support")
    [shimoda: split a patch per SoC and revise the commit log]
    Signed-off-by: Yoshihiro Shimoda's avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
    [geert: Use a macro to do the actual reordering]
    Signed-off-by: 's avatarGeert Uytterhoeven <geert+renesas@glider.be>
    Reviewed-by: 's avatarSimon Horman <horms+renesas@verge.net.au>
    5219aa33
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