1. 21 Feb, 2017 2 commits
  2. 12 Jan, 2017 1 commit
    • Russell King's avatar
      rtc: armada38x: make struct rtc_class_ops const · d748c981
      Russell King authored
      Armada38x wants to modify its rtc_class_ops to remove the interrupt
      handling when there is no usable interrupt, but this means we leave
      function pointers in writable memory.
      
      Since rtc_class_ops is small, arrange to have two instances, one for
      when we have interrupts, and one for when we have none, both marked
      const.  This allows the compiler to place them in read-only memory,
      which is better than placing them in __ro_after_init.
      
      Thanks to Bhumika Goyal <bhumirks@gmail.com> for pointing out that
      the structure was writable and submitting a patch to add
      __ro_after_init.
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
      d748c981
  3. 11 Jan, 2017 1 commit
    • Gregory CLEMENT's avatar
      rtc: armada38x: Follow the new recommendation for errata implementation · 844a3073
      Gregory CLEMENT authored
      According to RES-3124064:
      
      The device supports CPU write and read access to the RTC time register.
      However, due to this restriction, read and write from/to internal RTC
      register may fail.
      
      Workaround:
      General setup:
      1. Configure the RTC Mbus Bridge Timing Control register (offset 0x184A0)
         to value 0xFD4D4FFF
         Write RTC WRCLK Period to its maximum value (0x3FF)
         Write RTC WRCLK setup to 0x29
         Write RTC WRCLK High Time to 0x53 (default value)
         Write RTC Read Output Delay to its maximum value (0x1F)
         Mbus - Read All Byte Enable to 0x1 (default value)
      2. Configure the RTC Test Configuration Register (offset 0xA381C) bit3
         to '1' (Reserved, Marvell internal)
      
      For any RTC register read operation:
      1. Read the requested register 100 times.
      2. Find the result that appears most frequently and use this result
         as the correct value.
      
      For any RTC register write operation:
      1. Issue two dummy writes of 0x0 to the RTC Status register (offset
         0xA3800).
      2. Write the time to the RTC Time register (offset 0xA380C).
      
      This patch is based on the work of Shaker Daibes
      Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
      844a3073
  4. 05 Sep, 2015 2 commits
  5. 17 Jul, 2015 1 commit
  6. 15 May, 2015 1 commit
  7. 06 May, 2015 1 commit
  8. 14 Feb, 2015 1 commit