1. 08 Jun, 2018 17 commits
  2. 07 Jun, 2018 1 commit
    • Mark Brown's avatar
      regulator: gpio: Revert · e536700e
      Mark Brown authored
      regulator: fixed/gpio: Revert GPIO descriptor changes due to platform breakage
      
      Commit 6059577c "regulator: fixed: Convert to use GPIO descriptor
      only" broke at least the ams-delta platform since the lookup tables
      added to the board files use the function name "enable" while the driver
      uses NULL causing the regulator to not acquire and control the enable
      GPIOs.  Revert that and a couple of other commits that are caught up
      with it to fix the issue:
      
      2b6c00c1 "ARM: pxa, regulator: fix building ezx e680"
      6059577c "regulator: fixed: Convert to use GPIO descriptor only"
      37bed97f "regulator: gpio: Get enable GPIO using GPIO descriptor"
      Reported-by: default avatarJanusz Krzysztofik <jmkrzyszt@gmail.com>
      Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      e536700e
  3. 06 Jun, 2018 20 commits
    • Arnd Bergmann's avatar
      media: omap2: fix compile-testing with FB_OMAP2=m · 48a8bbc7
      Arnd Bergmann authored
      Compile-testing with FB_OMAP2=m results in a link error:
      
      drivers/media/platform/omap/omap_vout.o: In function `vidioc_streamoff':
      omap_vout.c:(.text+0x1028): undefined reference to `omap_dispc_unregister_isr'
      drivers/media/platform/omap/omap_vout.o: In function `omap_vout_release':
      omap_vout.c:(.text+0x1330): undefined reference to `omap_dispc_unregister_isr'
      drivers/media/platform/omap/omap_vout.o: In function `vidioc_streamon':
      omap_vout.c:(.text+0x2dd4): undefined reference to `omap_dispc_register_isr'
      drivers/media/platform/omap/omap_vout.o: In function `omap_vout_remove':
      
      In order to enable compile-testing but still keep the correct dependency,
      this changes the Kconfig logic so we only allow CONFIG_COMPILE_TEST
      building when FB_OMAP is completely disabled, or have use the old
      dependency on FB_OMAP to ensure VIDEO_OMAP2_VOUT is also a loadable
      module when FB_OMAP2 is.
      
      Fixes: d8555fd2 ("media: omap2: allow building it with COMPILE_TEST && DRM_OMAP")
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
      Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
      48a8bbc7
    • Kees Cook's avatar
      treewide: Use struct_size() for devm_kmalloc() and friends · 0ed2dd03
      Kees Cook authored
      Replaces open-coded struct size calculations with struct_size() for
      devm_*, f2fs_*, and sock_* allocations. Automatically generated (and
      manually adjusted) from the following Coccinelle script:
      
      // Direct reference to struct field.
      @@
      identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
      expression HANDLE;
      expression GFP;
      identifier VAR, ELEMENT;
      expression COUNT;
      @@
      
      - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP)
      + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)
      
      // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL);
      @@
      identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
      expression HANDLE;
      expression GFP;
      identifier VAR, ELEMENT;
      expression COUNT;
      @@
      
      - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP)
      + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)
      
      // Same pattern, but can't trivially locate the trailing element name,
      // or variable name.
      @@
      identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
      expression HANDLE;
      expression GFP;
      expression SOMETHING, COUNT, ELEMENT;
      @@
      
      - alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP)
      + alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP)
      Signed-off-by: default avatarKees Cook <keescook@chromium.org>
      0ed2dd03
    • Kees Cook's avatar
      treewide: Use struct_size() for vmalloc()-family · b4b06db1
      Kees Cook authored
      This only finds one hit in the entire tree, but here's the Coccinelle:
      
      // Directly refer to structure's field
      @@
      identifier alloc =~ "vmalloc|vzalloc";
      identifier VAR, ELEMENT;
      expression COUNT;
      @@
      
      - alloc(sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT))
      + alloc(struct_size(VAR, ELEMENT, COUNT))
      
      // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL);
      @@
      identifier alloc =~ "vmalloc|vzalloc";
      identifier VAR, ELEMENT;
      expression COUNT;
      @@
      
      - alloc(sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]))
      + alloc(struct_size(VAR, ELEMENT, COUNT))
      
      // Same pattern, but can't trivially locate the trailing element name,
      // or variable name.
      @@
      identifier alloc =~ "vmalloc|vzalloc";
      expression SOMETHING, COUNT, ELEMENT;
      @@
      
      - alloc(sizeof(SOMETHING) + COUNT * sizeof(ELEMENT))
      + alloc(CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT))
      Signed-off-by: default avatarKees Cook <keescook@chromium.org>
      b4b06db1
    • Kees Cook's avatar
      treewide: Use struct_size() for kmalloc()-family · acafe7e3
      Kees Cook authored
      One of the more common cases of allocation size calculations is finding
      the size of a structure that has a zero-sized array at the end, along
      with memory for some number of elements for that array. For example:
      
      struct foo {
          int stuff;
          void *entry[];
      };
      
      instance = kmalloc(sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL);
      
      Instead of leaving these open-coded and prone to type mistakes, we can
      now use the new struct_size() helper:
      
      instance = kmalloc(struct_size(instance, entry, count), GFP_KERNEL);
      
      This patch makes the changes for kmalloc()-family (and kvmalloc()-family)
      uses. It was done via automatic conversion with manual review for the
      "CHECKME" non-standard cases noted below, using the following Coccinelle
      script:
      
      // pkey_cache = kmalloc(sizeof *pkey_cache + tprops->pkey_tbl_len *
      //                      sizeof *pkey_cache->table, GFP_KERNEL);
      @@
      identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc";
      expression GFP;
      identifier VAR, ELEMENT;
      expression COUNT;
      @@
      
      - alloc(sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP)
      + alloc(struct_size(VAR, ELEMENT, COUNT), GFP)
      
      // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL);
      @@
      identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc";
      expression GFP;
      identifier VAR, ELEMENT;
      expression COUNT;
      @@
      
      - alloc(sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP)
      + alloc(struct_size(VAR, ELEMENT, COUNT), GFP)
      
      // Same pattern, but can't trivially locate the trailing element name,
      // or variable name.
      @@
      identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc";
      expression GFP;
      expression SOMETHING, COUNT, ELEMENT;
      @@
      
      - alloc(sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP)
      + alloc(CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP)
      Signed-off-by: default avatarKees Cook <keescook@chromium.org>
      acafe7e3
    • Xi Wang's avatar
      net: hns3: Optimize PF CMDQ interrupt switching process · 8e52a602
      Xi Wang authored
      When the PF frequently switches the CMDQ interrupt, if the CMDQ_SRC is
      not cleared before the hardware interrupt is generated, the new interrupt
      will not be reported.
      
      This patch optimizes this problem by clearing CMDQ_SRC and RESET_STS
      before enabling interrupt and syncing pending IRQ handlers after disabling
      interrupt.
      
      Fixes: 466b0c00 ("net: hns3: Add support for misc interrupt")
      Signed-off-by: default avatarXi Wang <wangxi11@huawei.com>
      Signed-off-by: default avatarPeng Li <lipeng321@huawei.com>
      Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8e52a602
    • Xi Wang's avatar
      net: hns3: Fix for VF mailbox receiving unknown message · 6444e2a5
      Xi Wang authored
      Before the firmware updates the crq's tail pointer, if the VF driver
      reads the data in the crq, the data may be incomplete at this time,
      which will lead to the driver read an unknown message.
      
      This patch fixes it by checking if crq is empty before reading the
      message.
      
      Fixes: b11a0bb2 ("net: hns3: Add mailbox support to VF driver")
      Signed-off-by: default avatarXi Wang <wangxi11@huawei.com>
      Signed-off-by: default avatarPeng Li <lipeng321@huawei.com>
      Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6444e2a5
    • Xi Wang's avatar
      net: hns3: Fix for VF mailbox cannot receiving PF response · 1819e409
      Xi Wang authored
      When the VF frequently switches the CMDQ interrupt, if the CMDQ_SRC is not
      cleared, the VF will not receive the new PF response after the interrupt
      is re-enabled, the corresponding log is as follows:
      
      [  317.482222] hns3 0000:00:03.0: VF could not get mbx resp(=0) from PF
      in 500 tries
      [  317.483137] hns3 0000:00:03.0: VF request to get tqp info from PF
      failed -5
      
      This patch fixes this problem by clearing CMDQ_SRC before enabling
      interrupt and syncing pending IRQ handlers after disabling interrupt.
      
      Fixes: e2cb1dec ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer) Support")
      Signed-off-by: default avatarXi Wang <wangxi11@huawei.com>
      Signed-off-by: default avatarPeng Li <lipeng321@huawei.com>
      Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      1819e409
    • Ross Zwisler's avatar
      dax: Use dax_write_cache* helpers · 808c340b
      Ross Zwisler authored
      Use dax_write_cache() and dax_write_cache_enabled() instead of open coding
      the bit operations.
      Signed-off-by: default avatarRoss Zwisler <ross.zwisler@linux.intel.com>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      808c340b
    • Ross Zwisler's avatar
      libnvdimm, pmem: Do not flush power-fail protected CPU caches · 546eb031
      Ross Zwisler authored
      This commit:
      
      5fdf8e5b ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
      
      intended to make sure that deep flush was always available even on
      platforms which support a power-fail protected CPU cache.  An unintended
      side effect of this change was that we also lost the ability to skip
      flushing CPU caches on those power-fail protected CPU cache.
      
      Fix this by skipping the low level cache flushing in dax_flush() if we have
      CPU caches which are power-fail protected.  The user can still override this
      behavior by manually setting the write_cache state of a namespace.  See
      libndctl's ndctl_namespace_write_cache_is_enabled(),
      ndctl_namespace_enable_write_cache() and
      ndctl_namespace_disable_write_cache() functions.
      
      Cc: <stable@vger.kernel.org>
      Fixes: 5fdf8e5b ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
      Signed-off-by: default avatarRoss Zwisler <ross.zwisler@linux.intel.com>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      546eb031
    • Julia Lawall's avatar
      bnx2x: use the right constant · dd612f18
      Julia Lawall authored
      Nearby code that also tests port suggests that the P0 constant should be
      used when port is zero.
      
      The semantic match that finds this problem is as follows:
      (http://coccinelle.lip6.fr/)
      
      // <smpl>
      @@
      expression e,e1;
      @@
      
      * e ? e1 : e1
      // </smpl>
      
      Fixes: 6c3218c6 ("bnx2x: Adjust ETS to 578xx")
      Signed-off-by: default avatarJulia Lawall <Julia.Lawall@lip6.fr>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      dd612f18
    • Ross Zwisler's avatar
      libnvdimm, pmem: Unconditionally deep flush on *sync · ce7f11a2
      Ross Zwisler authored
      Prior to this commit we would only do a "deep flush" (have nvdimm_flush()
      write to each of the flush hints for a region) in response to an
      msync/fsync/sync call if the nvdimm_has_cache() returned true at the time
      we were setting up the request queue.  This happens due to the write cache
      value passed in to blk_queue_write_cache(), which then causes the block
      layer to send down BIOs with REQ_FUA and REQ_PREFLUSH set.  We do have a
      "write_cache" sysfs entry for namespaces, i.e.:
      
        /sys/bus/nd/devices/pfn0.1/block/pmem0/dax/write_cache
      
      which can be used to control whether or not the kernel thinks a given
      namespace has a write cache, but this didn't modify the deep flush behavior
      that we set up when the driver was initialized.  Instead, it only modified
      whether or not DAX would flush CPU caches via dax_flush() in response to
      *sync calls.
      
      Simplify this by making the *sync deep flush always happen, regardless of
      the write cache setting of a namespace.  The DAX CPU cache flushing will
      still be controlled the write_cache setting of the namespace.
      
      Cc: <stable@vger.kernel.org>
      Fixes: 5fdf8e5b ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
      Signed-off-by: default avatarRoss Zwisler <ross.zwisler@linux.intel.com>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      ce7f11a2
    • Arun Parameswaran's avatar
      net: dsa: b53: Fix for brcm tag issue in Cygnus SoC · 5040cc99
      Arun Parameswaran authored
      In the Broadcom Cygnus SoC, the brcm tag needs to be inserted
      in between the mac address and the ether type (should use
      'DSA_PROTO_TAG_BRCM') for the packets sent to the internal
      b53 switch.
      
      Since the Cygnus was added with the BCM58XX device id and the
      BCM58XX uses 'DSA_PROTO_TAG_BRCM_PREPEND', the data path is
      broken, due to the incorrect brcm tag location.
      
      Add a new b53 device id (BCM583XX) for Cygnus family to fix the
      issue. Add the new device id to the BCM58XX family as Cygnus
      is similar to the BCM58XX in most other functionalities.
      
      Fixes: 11606039 ("net: dsa: b53: Support prepended Broadcom tags")
      Signed-off-by: default avatarArun Parameswaran <arun.parameswaran@broadcom.com>
      Acked-by: default avatarScott Branden <scott.branden@broadcom.com>
      Reported-by: Clément Péron's avatarClément Péron <peron.clem@gmail.com>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Tested-by: Clément Péron's avatarClément Péron <peron.clem@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5040cc99
    • Ross Zwisler's avatar
      libnvdimm, pmem: Complete REQ_FLUSH => REQ_PREFLUSH · d2d6364d
      Ross Zwisler authored
      Complete the move from REQ_FLUSH to REQ_PREFLUSH that apparently started
      way back in v4.8.
      Signed-off-by: default avatarRoss Zwisler <ross.zwisler@linux.intel.com>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      d2d6364d
    • Daniel Lezcano's avatar
      mailbox/drivers/hisi: Consolidate the Kconfig for the MAILBOX · f83d1cfc
      Daniel Lezcano authored
      The current defconfig is inconsistent as it selects the mailbox and
      the clock for the hi6220 and the hi3660 without having their Kconfigs
      making sure the dependencies are correct. It ends up when selecting
      different versions for the kernel (for example when git bisecting)
      those options disappear and they don't get back, leading to unexpected
      behaviors. In our case, the cpufreq driver does no longer work because
      the clock fails to initialize due to the clock stub and the mailbox
      missing.
      
      In order to have the dependencies correctly set when defaulting, let's
      do the same as commit 3a49afb8 ("clk: enable hi655x common clk
      automatically") where we select automatically the driver when the
      parent driver is selected. With sensible defaults in place, we can leave
      other choices for EXPERT.
      Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
      Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
      Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
      f83d1cfc
    • Sibi Sankar's avatar
      mailbox: Add support for Qualcomm SDM845 SoCs · 05e99a7d
      Sibi Sankar authored
      Add the corresponding APSS shared offset for SDM845 SoC
      Signed-off-by: default avatarSibi Sankar <sibis@codeaurora.org>
      Reviewed-by: Bjorn Andersson's avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
      05e99a7d
    • Stefan Wahren's avatar
      mailbox: bcm2835: Fix of_xlate return value · 00ee3a13
      Stefan Wahren authored
      The bcm2835-mailbox returns NULL instead of an error pointer, which could
      result in a NULL ptr dereference in mbox_request_channel. So fix this
      by returning a proper error pointer.
      Signed-off-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
      Fixes: 0bae6af6 ("mailbox: Enable BCM2835 mailbox support")
      Reviewed-by: Eric Anholt's avatarEric Anholt <eric@anholt.net>
      Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
      00ee3a13
    • Bjorn Andersson's avatar
      mailbox: qcom: Add msm8998 hmss compatible · 61a2f6db
      Bjorn Andersson authored
      The Qualcomm MSM8998 platform has a APCS HMSS GLOBAL block, add the
      compatible for this.
      Signed-off-by: Bjorn Andersson's avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Reviewed-by: Rob Herring's avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
      61a2f6db
    • Fabien Dessenne's avatar
      mailbox: add STMicroelectronics STM32 IPCC driver · ffbded7d
      Fabien Dessenne authored
      The STMicroelectronics STM32 Inter-Processor Communication Controller
      (IPCC) is used for communicating data between two processors.
      It provides a non blocking signaling mechanism to post and retrieve
      communication data in an atomic way.
      Signed-off-by: default avatarFabien Dessenne <fabien.dessenne@st.com>
      Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
      Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
      ffbded7d
    • Geert Uytterhoeven's avatar
      mailbox: Remove depends on HAS_DMA in case of platform dependency · 19ed70c0
      Geert Uytterhoeven authored
      Remove dependencies on HAS_DMA where a Kconfig symbol depends on another
      symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST".
      In most cases this other symbol is an architecture or platform specific
      symbol, or PCI.
      
      Generic symbols and drivers without platform dependencies keep their
      dependencies on HAS_DMA, to prevent compiling subsystems or drivers that
      cannot work anyway.
      
      This simplifies the dependencies, and allows to improve compile-testing.
      Signed-off-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
      Reviewed-by: default avatarMark Brown <broonie@kernel.org>
      Acked-by: default avatarRobin Murphy <robin.murphy@arm.com>
      Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
      19ed70c0
    • Govindarajulu Varadarajan's avatar
      enic: fix UDP rss bits · 4016a7f1
      Govindarajulu Varadarajan authored
      In commit 48398b6e ("enic: set UDP rss flag") driver needed to set a
      single bit to enable UDP rss. This is changed to two bit. One for UDP
      IPv4 and other bit for UDP IPv6. The hardware which supports this is not
      released yet. When released, driver should set 2 bit to enable UDP rss for
      both IPv4 and IPv6.
      
      Also add spinlock around vnic_dev_capable_rss_hash_type().
      Signed-off-by: default avatarGovindarajulu Varadarajan <gvaradar@cisco.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4016a7f1
  4. 05 Jun, 2018 2 commits