Commit 75eaff01 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
 - BMIPS SMP fixes
 - a build fix necessary for older compilers
 - two more bugs found my Chandras' testing
 - and one more build fix

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: BMIPS: fix slave CPU booting when physical CPU is not 0
  MIPS: BMIPS: do not change interrupt routing depending on boot CPU
  MIPS: powertv: Fix arguments for free_reserved_area()
  MIPS: Set default CPU type for BCM47XX platforms
  MIPS: uapi/asm/siginfo.h: Fix GCC 4.1.2 compilation
  MIPS: Fix multiple definitions of UNCAC_BASE.
parents f66d95d6 ff5fadaf
......@@ -114,6 +114,7 @@ config BCM47XX
select FW_CFE
select HW_HAS_PCI
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select NO_EXCEPT_FILL
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
......
......@@ -2,7 +2,6 @@ if BCM47XX
config BCM47XX_SSB
bool "SSB Support for Broadcom BCM47XX"
select SYS_HAS_CPU_MIPS32_R1
select SSB
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
......
......@@ -25,8 +25,12 @@
#else
#define CAC_BASE _AC(0x80000000, UL)
#endif
#ifndef IO_BASE
#define IO_BASE _AC(0xa0000000, UL)
#endif
#ifndef UNCAC_BASE
#define UNCAC_BASE _AC(0xa0000000, UL)
#endif
#ifndef MAP_BASE
#ifdef CONFIG_KVM_GUEST
......
......@@ -25,11 +25,12 @@ struct siginfo;
/*
* Careful to keep union _sifields from shifting ...
*/
#if __SIZEOF_LONG__ == 4
#if _MIPS_SZLONG == 32
#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
#endif
#if __SIZEOF_LONG__ == 8
#elif _MIPS_SZLONG == 64
#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
#else
#error _MIPS_SZLONG neither 32 nor 64
#endif
#include <asm-generic/siginfo.h>
......
......@@ -54,7 +54,11 @@ LEAF(bmips_smp_movevec)
/* set up CPU1 CBR; move BASE to 0xa000_0000 */
li k0, 0xff400000
mtc0 k0, $22, 6
li k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1
/* set up relocation vector address based on thread ID */
mfc0 k1, $22, 3
srl k1, 16
andi k1, 0x8000
or k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
or k0, k1
li k1, 0xa0080000
sw k1, 0(k0)
......
......@@ -79,15 +79,9 @@ static void __init bmips_smp_setup(void)
* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
*
* If booting from TP1, leave the existing CMT interrupt routing
* such that TP0 responds to SW1 and TP1 responds to SW0.
*/
if (boot_cpu == 0)
change_c0_brcm_cmt_intr(0xf8018000,
change_c0_brcm_cmt_intr(0xf8018000,
(0x02 << 27) | (0x03 << 15));
else
change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
/* single core, 2 threads (2 pipelines) */
max_cpus = 2;
......@@ -202,9 +196,15 @@ static void bmips_init_secondary(void)
#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
void __iomem *cbr = BMIPS_GET_CBR();
unsigned long old_vec;
unsigned long relo_vector;
int boot_cpu;
boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
BMIPS_RELO_VECTOR_CONTROL_1;
old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
__raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
old_vec = __raw_readl(cbr + relo_vector);
__raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
#elif defined(CONFIG_CPU_BMIPS5000)
......
......@@ -529,8 +529,7 @@ EXPORT_SYMBOL(asic_resource_get);
*/
void platform_release_memory(void *ptr, int size)
{
free_reserved_area((unsigned long)ptr, (unsigned long)(ptr + size),
-1, NULL);
free_reserved_area(ptr, ptr + size, -1, NULL);
}
EXPORT_SYMBOL(platform_release_memory);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment