Commit 3f8c50c9 authored by John Crispin's avatar John Crispin

OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support

Implement support for pinctrl on lantiq/xway socs. The IO core found on these
socs has the registers for pinctrl, pinconf and gpio mixed up in the same
register range. As the gpio_chip handling is only a few lines, the driver also
implements the gpio functionality. This obseletes the old gpio driver that was
located in the arch/ folder.
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
parent 30404aec
......@@ -241,6 +241,8 @@ config LANTIQ
select HAVE_MACH_CLKDEV
select CLKDEV_LOOKUP
select USE_OF
select PINCTRL
select PINCTRL_LANTIQ
config LASAT
bool "LASAT Networks platforms"
......
......@@ -2,6 +2,7 @@ if LANTIQ
config SOC_TYPE_XWAY
bool
select PINCTRL_XWAY
default n
choice
......
obj-y := prom.o sysctrl.o clk.o reset.o gpio.o dma.o gptu.o
obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <lantiq_soc.h>
#define LTQ_GPIO_OUT 0x00
#define LTQ_GPIO_IN 0x04
#define LTQ_GPIO_DIR 0x08
#define LTQ_GPIO_ALTSEL0 0x0C
#define LTQ_GPIO_ALTSEL1 0x10
#define LTQ_GPIO_OD 0x14
#define PINS_PER_PORT 16
#define MAX_PORTS 3
#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r)
#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r)
struct ltq_gpio {
void __iomem *membase;
struct gpio_chip chip;
};
static struct ltq_gpio ltq_gpio_port[MAX_PORTS];
int ltq_gpio_request(unsigned int pin, unsigned int alt0,
unsigned int alt1, unsigned int dir, const char *name)
{
int id = 0;
if (pin >= (MAX_PORTS * PINS_PER_PORT))
return -EINVAL;
if (gpio_request(pin, name)) {
pr_err("failed to setup lantiq gpio: %s\n", name);
return -EBUSY;
}
if (dir)
gpio_direction_output(pin, 1);
else
gpio_direction_input(pin);
while (pin >= PINS_PER_PORT) {
pin -= PINS_PER_PORT;
id++;
}
if (alt0)
ltq_gpio_setbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL0, pin);
else
ltq_gpio_clearbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL0, pin);
if (alt1)
ltq_gpio_setbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL1, pin);
else
ltq_gpio_clearbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL1, pin);
return 0;
}
EXPORT_SYMBOL(ltq_gpio_request);
static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
if (value)
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
else
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
}
static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset);
}
static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
return 0;
}
static int ltq_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
ltq_gpio_set(chip, offset, value);
return 0;
}
static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset)
{
struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
return 0;
}
static int ltq_gpio_probe(struct platform_device *pdev)
{
struct resource *res;
if (pdev->id >= MAX_PORTS) {
dev_err(&pdev->dev, "invalid gpio port %d\n",
pdev->id);
return -EINVAL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
pdev->id);
return -ENOENT;
}
res = devm_request_mem_region(&pdev->dev, res->start,
resource_size(res), dev_name(&pdev->dev));
if (!res) {
dev_err(&pdev->dev,
"failed to request memory for gpio port %d\n",
pdev->id);
return -EBUSY;
}
ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev,
res->start, resource_size(res));
if (!ltq_gpio_port[pdev->id].membase) {
dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n",
pdev->id);
return -ENOMEM;
}
ltq_gpio_port[pdev->id].chip.label = "ltq_gpio";
ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input;
ltq_gpio_port[pdev->id].chip.direction_output =
ltq_gpio_direction_output;
ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get;
ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
}
static struct platform_driver
ltq_gpio_driver = {
.probe = ltq_gpio_probe,
.driver = {
.name = "ltq_gpio",
.owner = THIS_MODULE,
},
};
int __init ltq_gpio_init(void)
{
int ret = platform_driver_register(&ltq_gpio_driver);
if (ret)
pr_info("ltq_gpio : Error registering platform driver!");
return ret;
}
postcore_initcall(ltq_gpio_init);
......@@ -55,6 +55,12 @@ config PINCTRL_IMX6Q
help
Say Y here to enable the imx6q pinctrl driver
config PINCTRL_LANTIQ
bool
depends on LANTIQ
select PINMUX
select PINCONF
config PINCTRL_PXA3xx
bool
select PINMUX
......@@ -147,6 +153,11 @@ config PINCTRL_COH901
source "drivers/pinctrl/spear/Kconfig"
config PINCTRL_XWAY
bool
depends on SOC_TYPE_XWAY
depends on PINCTRL_LANTIQ
endmenu
endif
......@@ -29,5 +29,7 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
/*
* linux/drivers/pinctrl/pinctrl-lantiq.c
* based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*
* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include "pinctrl-lantiq.h"
static int ltq_get_group_count(struct pinctrl_dev *pctrldev)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
return info->num_grps;
}
static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev,
unsigned selector)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
if (selector >= info->num_grps)
return NULL;
return info->grps[selector].name;
}
static int ltq_get_group_pins(struct pinctrl_dev *pctrldev,
unsigned selector,
const unsigned **pins,
unsigned *num_pins)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
if (selector >= info->num_grps)
return -EINVAL;
*pins = info->grps[selector].pins;
*num_pins = info->grps[selector].npins;
return 0;
}
void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; i++)
if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
kfree(map[i].data.configs.configs);
kfree(map);
}
static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
unsigned long configs[3];
unsigned num_configs = 0;
struct property *prop;
const char *group, *pin;
const char *function;
int ret, i;
ret = of_property_read_string(np, "lantiq,function", &function);
if (!ret) {
of_property_for_each_string(np, "lantiq,groups", prop, group) {
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->name = function;
(*map)->data.mux.group = group;
(*map)->data.mux.function = function;
(*map)++;
}
if (of_find_property(np, "lantiq,pins", NULL))
dev_err(pctldev->dev,
"%s mixes pins and groups settings\n",
np->name);
return 0;
}
for (i = 0; i < info->num_params; i++) {
u32 val;
int ret = of_property_read_u32(np,
info->params[i].property, &val);
if (!ret)
configs[num_configs++] =
LTQ_PINCONF_PACK(info->params[i].param,
val);
}
if (!num_configs)
return -EINVAL;
of_property_for_each_string(np, "lantiq,pins", prop, pin) {
(*map)->data.configs.configs = kmemdup(configs,
num_configs * sizeof(unsigned long),
GFP_KERNEL);
(*map)->type = PIN_MAP_TYPE_CONFIGS_PIN;
(*map)->name = pin;
(*map)->data.configs.group_or_pin = pin;
(*map)->data.configs.num_configs = num_configs;
(*map)++;
}
return 0;
}
static int ltq_pinctrl_dt_subnode_size(struct device_node *np)
{
int ret;
ret = of_property_count_strings(np, "lantiq,groups");
if (ret < 0)
ret = of_property_count_strings(np, "lantiq,pins");
return ret;
}
int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned *num_maps)
{
struct pinctrl_map *tmp;
struct device_node *np;
int ret;
*num_maps = 0;
for_each_child_of_node(np_config, np)
*num_maps += ltq_pinctrl_dt_subnode_size(np);
*map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
if (!*map)
return -ENOMEM;
tmp = *map;
for_each_child_of_node(np_config, np) {
ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
if (ret < 0) {
ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps);
return ret;
}
}
return 0;
}
static struct pinctrl_ops ltq_pctrl_ops = {
.get_groups_count = ltq_get_group_count,
.get_group_name = ltq_get_group_name,
.get_group_pins = ltq_get_group_pins,
.pin_dbg_show = ltq_pinctrl_pin_dbg_show,
.dt_node_to_map = ltq_pinctrl_dt_node_to_map,
.dt_free_map = ltq_pinctrl_dt_free_map,
};
static int ltq_pmx_func_count(struct pinctrl_dev *pctrldev)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
return info->num_funcs;
}
static const char *ltq_pmx_func_name(struct pinctrl_dev *pctrldev,
unsigned selector)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
if (selector >= info->num_funcs)
return NULL;
return info->funcs[selector].name;
}
static int ltq_pmx_get_groups(struct pinctrl_dev *pctrldev,
unsigned func,
const char * const **groups,
unsigned * const num_groups)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
*groups = info->funcs[func].groups;
*num_groups = info->funcs[func].num_groups;
return 0;
}
/* Return function number. If failure, return negative value. */
static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux)
{
int i;
for (i = 0; i < LTQ_MAX_MUX; i++) {
if (mfp->func[i] == mux)
break;
}
if (i >= LTQ_MAX_MUX)
return -EINVAL;
return i;
}
/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */
static int match_mfp(const struct ltq_pinmux_info *info, int pin)
{
int i;
for (i = 0; i < info->num_mfp; i++) {
if (info->mfp[i].pin == pin)
return i;
}
return -1;
}
/* check whether current pin configuration is valid. Negative for failure */
static int match_group_mux(const struct ltq_pin_group *grp,
const struct ltq_pinmux_info *info,
unsigned mux)
{
int i, pin, ret = 0;
for (i = 0; i < grp->npins; i++) {
pin = match_mfp(info, grp->pins[i]);
if (pin < 0) {
dev_err(info->dev, "could not find mfp for pin %d\n",
grp->pins[i]);
return -EINVAL;
}
ret = match_mux(&info->mfp[pin], mux);
if (ret < 0) {
dev_err(info->dev, "Can't find mux %d on pin%d\n",
mux, pin);
break;
}
}
return ret;
}
static int ltq_pmx_enable(struct pinctrl_dev *pctrldev,
unsigned func,
unsigned group)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
const struct ltq_pin_group *pin_grp = &info->grps[group];
int i, pin, pin_func, ret;
if (!pin_grp->npins ||
(match_group_mux(pin_grp, info, pin_grp->mux) < 0)) {
dev_err(info->dev, "Failed to set the pin group: %s\n",
info->grps[group].name);
return -EINVAL;
}
for (i = 0; i < pin_grp->npins; i++) {
pin = match_mfp(info, pin_grp->pins[i]);
if (pin < 0) {
dev_err(info->dev, "could not find mfp for pin %d\n",
pin_grp->pins[i]);
return -EINVAL;
}
pin_func = match_mux(&info->mfp[pin], pin_grp->mux);
ret = info->apply_mux(pctrldev, pin, pin_func);
if (ret) {
dev_err(info->dev,
"failed to apply mux %d for pin %d\n",
pin_func, pin);
return ret;
}
}
return 0;
}
static void ltq_pmx_disable(struct pinctrl_dev *pctrldev,
unsigned func,
unsigned group)
{
/*
* Nothing to do here. However, pinconf_check_ops() requires this
* callback to be defined.
*/
}
static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
struct pinctrl_gpio_range *range,
unsigned pin)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
int mfp = match_mfp(info, pin + (range->id * 32));
int pin_func;
if (mfp < 0) {
dev_err(info->dev, "could not find mfp for pin %d\n", pin);
return -EINVAL;
}
pin_func = match_mux(&info->mfp[mfp], 0);
if (pin_func < 0) {
dev_err(info->dev, "No GPIO function on pin%d\n", mfp);
return -EINVAL;
}
return info->apply_mux(pctrldev, mfp, pin_func);
}
static struct pinmux_ops ltq_pmx_ops = {
.get_functions_count = ltq_pmx_func_count,
.get_function_name = ltq_pmx_func_name,
.get_function_groups = ltq_pmx_get_groups,
.enable = ltq_pmx_enable,
.disable = ltq_pmx_disable,
.gpio_request_enable = ltq_pmx_gpio_request_enable,
};
/*
* allow different socs to register with the generic part of the lanti
* pinctrl code
*/
int ltq_pinctrl_register(struct platform_device *pdev,
struct ltq_pinmux_info *info)
{
struct pinctrl_desc *desc;
if (!info)
return -EINVAL;
desc = info->desc;
desc->pctlops = &ltq_pctrl_ops;
desc->pmxops = &ltq_pmx_ops;
info->dev = &pdev->dev;
info->pctrl = pinctrl_register(desc, &pdev->dev, info);
if (!info->pctrl) {
dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n");
return -EINVAL;
}
platform_set_drvdata(pdev, info);
return 0;
}
/*
* linux/drivers/pinctrl/pinctrl-lantiq.h
* based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*
* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
*/
#ifndef __PINCTRL_LANTIQ_H
#include <linux/clkdev.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include "core.h"
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
#define LTQ_MAX_MUX 4
#define MFPR_FUNC_MASK 0x3
#define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg))
#define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16)
#define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff)
enum ltq_pinconf_param {
LTQ_PINCONF_PARAM_PULL,
LTQ_PINCONF_PARAM_OPEN_DRAIN,
LTQ_PINCONF_PARAM_DRIVE_CURRENT,
LTQ_PINCONF_PARAM_SLEW_RATE,
};
struct ltq_cfg_param {
const char *property;
enum ltq_pinconf_param param;
};
struct ltq_mfp_pin {
const char *name;
const unsigned int pin;
const unsigned short func[LTQ_MAX_MUX];
};
struct ltq_pin_group {
const char *name;
const unsigned mux;
const unsigned *pins;
const unsigned npins;
};
struct ltq_pmx_func {
const char *name;
const char * const *groups;
const unsigned num_groups;
};
struct ltq_pinmux_info {
struct device *dev;
struct pinctrl_dev *pctrl;
/* we need to manage up to 5 pad controllers */
void __iomem *membase[5];
/* the descriptor for the subsystem */
struct pinctrl_desc *desc;
/* we expose our pads to the subsystem */
struct pinctrl_pin_desc *pads;
/* the number of pads. this varies between socs */
unsigned int num_pads;
/* these are our multifunction pins */
const struct ltq_mfp_pin *mfp;
unsigned int num_mfp;
/* a number of multifunction pins can be grouped together */
const struct ltq_pin_group *grps;
unsigned int num_grps;
/* a mapping between function string and id */
const struct ltq_pmx_func *funcs;
unsigned int num_funcs;
/* the pinconf options that we are able to read from the DT */
const struct ltq_cfg_param *params;
unsigned int num_params;
/* the pad controller can have a irq mapping */
const unsigned *exin;
unsigned int num_exin;
/* we need 5 clocks max */
struct clk *clk[5];
/* soc specific callback used to apply muxing */
int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
};
enum ltq_pin {
GPIO0 = 0,
GPIO1,
GPIO2,
GPIO3,
GPIO4,
GPIO5,
GPIO6,
GPIO7,
GPIO8,
GPIO9,
GPIO10, /* 10 */
GPIO11,
GPIO12,
GPIO13,
GPIO14,
GPIO15,
GPIO16,
GPIO17,
GPIO18,
GPIO19,
GPIO20, /* 20 */
GPIO21,
GPIO22,
GPIO23,
GPIO24,
GPIO25,
GPIO26,
GPIO27,
GPIO28,
GPIO29,
GPIO30, /* 30 */
GPIO31,
GPIO32,
GPIO33,
GPIO34,
GPIO35,
GPIO36,
GPIO37,
GPIO38,
GPIO39,
GPIO40, /* 40 */
GPIO41,
GPIO42,
GPIO43,