• Katsuhiro Suzuki's avatar
    clk: rockchip: fix frac settings of GPLL clock for rk3328 · e84e0a8c
    Katsuhiro Suzuki authored
    [ Upstream commit a0e447b0 ]
    
    This patch fixes settings of GPLL frequency in fractional mode for
    rk3328. In this mode, FOUTVCO is calcurated by following formula:
      FOUTVCO = FREF * FBDIV / REFDIV + ((FREF * FRAC / REFDIV) >> 24)
    
    The problem is in FREF * FRAC >> 24 term. This result always lacks
    one from target value is specified by rate member. For example first
    itme of rk3328_pll_frac_rate originally has
      - rate  : 1016064000
      - refdiv: 3
      - fbdiv : 127
      - frac  : 134217
      - FREF * FBDIV / REFDIV        = 1016000000
      - (FREF * FRAC / REFDIV) >> 24 = 63999
    Thus calculated rate is 1016063999. It seems wrong.
    
    If frac has 134218 (it is increased 1 from original value), second
    term is 64000. All other items have same situation. So this patch
    adds 1 to frac member in all items of rk3328_pll_frac_rate.
    Signed-off-by: 's avatarKatsuhiro Suzuki <katsuhiro@katsuster.net>
    Acked-by: 's avatarElaine Zhang <zhangqing@rock-chips.com>
    Signed-off-by: 's avatarHeiko Stuebner <heiko@sntech.de>
    Signed-off-by: 's avatarSasha Levin <sashal@kernel.org>
    e84e0a8c
clk-rk3328.c 37 KB