• Eugeniy Paltsev's avatar
    clk: axs10x: introduce AXS10X pll driver · 6d7489c7
    Eugeniy Paltsev authored
    AXS10X boards manages it's clocks using various PLLs. These PLL has same
    dividers and corresponding control registers mapped to different addresses.
    So we add one common driver for such PLLs.
    Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
    ODIV. Output clock value is managed using these dividers.
    We add pre-defined tables with supported rate values and appropriate
    configurations of IDIV, FBDIV and ODIV for each value.
    As of today we add support for PLLs that generate clock for the
    following devices:
     * ARC core on AXC CPU tiles.
     * ARC PGU on ARC SDP Mainboard.
    and more to come later.
    By this patch we add support for two plls (arc core pll and pgu pll),
    so we had to use two different init types: CLK_OF_DECLARE for arc core pll and
    regular probing for pgu pll.
    Acked-by: Rob Herring's avatarRob Herring <robh@kernel.org>
    Acked-by: 's avatarJose Abreu <joabreu@synopsys.com>
    Signed-off-by: 's avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
    Signed-off-by: 's avatarVlad Zakharov <vzakhar@synopsys.com>
    Signed-off-by: 's avatarJose Abreu <joabreu@synopsys.com>
    [sboyd@codeaurora.org: Silence dubious !x & y sparse warning,
    make of_axs10x_pll_clk_setup() unregister clk on failure]
    Signed-off-by: 's avatarStephen Boyd <sboyd@codeaurora.org>
Makefile 46 Bytes