• Vignesh R's avatar
    phy: phy-ti-pipe3: fix inconsistent enumeration of PCIe gen2 cards · 0bc09f9c
    Vignesh R authored
    Prior to DRA74x silicon rev 1.1, pcie_pcs register bits 8-15 and bits 16-23
    were used to configure RC delay count for phy1 and phy2 respectively.
    phyid was used as index to distinguish the phys and to configure the delay
    values appropriately.
    
    As of DRA74x silicon rev 1.1, pcie_pcs register definition has changed.
    Bits 16-23 are used to configure delay values for *both* phy1 and phy2.
    
    Hence phyid is no longer required.
    
    So, drop id field from ti_pipe3 structure and its subsequent references
    for configuring pcie_pcs register.
    
    Also, pcie_pcs register now needs to be configured with delay value of 0x96
    at bit positions 16-23. See register description of CTRL_CORE_PCIE_PCS in
    ARM572x TRM, SPRUHZ6, October 2014, section 18.5.2.2, table 18-1804.
    
    This is needed to ensure Gen2 cards are enumerated consistently.
    
    DRA72x silicon behaves same way as DRA74x rev 1.1 as far as this functionality
    is considered.
    
    Test results on DRA74x and DRA72x EVMs:
    
    Before patch
    ------------
    DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to
    silicon errata)
    DRA74x ES 1.1: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect
    programming of register
    
    DRA72x: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect
    programming of register
    
    After patch
    -----------
    DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to
    silicon errata)
    DRA74x ES 1.1: Gen1 cards work, Gen2 cards work consistently.
    
    DRA72x: Gen1 and Gen2 cards enumerate consistently.
    Signed-off-by: default avatarVignesh R <vigneshr@ti.com>
    Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
    0bc09f9c
omap_control_phy.h 2.85 KB