• Jan Luebbe's avatar
    bus: mbus: fix window size calculation for 4GB windows · 2bbbd963
    Jan Luebbe authored
    At least the Armada XP SoC supports 4GB on a single DRAM window. Because
    the size register values contain the actual size - 1, the MSB is set in
    that case. For example, the SDRAM window's control register's value is
    0xffffffe1 for 4GB (bits 31 to 24 contain the size).
    The MBUS driver reads back each window's size from registers and
    calculates the actual size as (control_reg | ~DDR_SIZE_MASK) + 1, which
    overflows for 32 bit values, resulting in other miscalculations further
    on (a bad RAM window for the CESA crypto engine calculated by
    mvebu_mbus_setup_cpu_target_nooverlap() in my case).
    This patch changes the type in 'struct mbus_dram_window' from u32 to
    u64, which allows us to keep using the same register calculation code in
    most MBUS-using drivers (which calculate ->size - 1 again).
    Fixes: fddddb52 ("bus: introduce an Marvell EBU MBus driver")
    CC: stable@vger.kernel.org
    Signed-off-by: default avatarJan Luebbe <jlu@pengutronix.de>
    Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
mbus.h 3.09 KB