pinctrl-at91.c 48.7 KB
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/*
 * at91 pinctrl driver based on at91 pinmux core
 *
 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * Under GPLv2 only
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/io.h>
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#include <linux/gpio/driver.h>
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#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>

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#include "pinctrl-at91.h"
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#include "core.h"

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#define MAX_GPIO_BANKS		5
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#define MAX_NB_GPIO_PER_BANK	32

struct at91_pinctrl_mux_ops;

struct at91_gpio_chip {
	struct gpio_chip	chip;
	struct pinctrl_gpio_range range;
	struct at91_gpio_chip	*next;		/* Bank sharing same clock */
	int			pioc_hwirq;	/* PIO bank interrupt identifier on AIC */
	int			pioc_virq;	/* PIO bank Linux virtual interrupt */
	int			pioc_idx;	/* PIO bank index */
	void __iomem		*regbase;	/* PIO bank virtual address */
	struct clk		*clock;		/* associated clock */
	struct at91_pinctrl_mux_ops *ops;	/* ops */
};

static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];

static int gpio_banks;

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#define PULL_UP		(1 << 0)
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#define MULTI_DRIVE	(1 << 1)
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#define DEGLITCH	(1 << 2)
#define PULL_DOWN	(1 << 3)
#define DIS_SCHMIT	(1 << 4)
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#define DRIVE_STRENGTH_SHIFT	5
#define DRIVE_STRENGTH_MASK		0x3
#define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
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#define OUTPUT		(1 << 7)
#define OUTPUT_VAL_SHIFT	8
#define OUTPUT_VAL	(0x1 << OUTPUT_VAL_SHIFT)
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#define DEBOUNCE	(1 << 16)
#define DEBOUNCE_VAL_SHIFT	17
#define DEBOUNCE_VAL	(0x3fff << DEBOUNCE_VAL_SHIFT)
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/**
 * These defines will translated the dt binding settings to our internal
 * settings. They are not necessarily the same value as the register setting.
 * The actual drive strength current of low, medium and high must be looked up
 * from the corresponding device datasheet. This value is different for pins
 * that are even in the same banks. It is also dependent on VCC.
 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
 * strength when there is no dt config for it.
 */
#define DRIVE_STRENGTH_DEFAULT		(0 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_LOW          (1 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_MED          (2 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_HI           (3 << DRIVE_STRENGTH_SHIFT)

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/**
 * struct at91_pmx_func - describes AT91 pinmux functions
 * @name: the name of this specific function
 * @groups: corresponding pin groups
 * @ngroups: the number of groups
 */
struct at91_pmx_func {
	const char	*name;
	const char	**groups;
	unsigned	ngroups;
};

enum at91_mux {
	AT91_MUX_GPIO = 0,
	AT91_MUX_PERIPH_A = 1,
	AT91_MUX_PERIPH_B = 2,
	AT91_MUX_PERIPH_C = 3,
	AT91_MUX_PERIPH_D = 4,
};

/**
 * struct at91_pmx_pin - describes an At91 pin mux
 * @bank: the bank of the pin
 * @pin: the pin number in the @bank
 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
 */
struct at91_pmx_pin {
	uint32_t	bank;
	uint32_t	pin;
	enum at91_mux	mux;
	unsigned long	conf;
};

/**
 * struct at91_pin_group - describes an At91 pin group
 * @name: the name of this specific pin group
 * @pins_conf: the mux mode for each pin in this group. The size of this
 *	array is the same as pins.
 * @pins: an array of discrete physical pins used in this group, taken
 *	from the driver-local pin enumeration space
 * @npins: the number of pins in this group array, i.e. the number of
 *	elements in .pins so we can iterate over that array
 */
struct at91_pin_group {
	const char		*name;
	struct at91_pmx_pin	*pins_conf;
	unsigned int		*pins;
	unsigned		npins;
};

/**
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 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
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 * on new IP with support for periph C and D the way to mux in
 * periph A and B has changed
 * So provide the right call back
 * if not present means the IP does not support it
 * @get_periph: return the periph mode configured
 * @mux_A_periph: mux as periph A
 * @mux_B_periph: mux as periph B
 * @mux_C_periph: mux as periph C
 * @mux_D_periph: mux as periph D
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 * @get_deglitch: get deglitch status
 * @set_deglitch: enable/disable deglitch
 * @get_debounce: get debounce status
 * @set_debounce: enable/disable debounce
 * @get_pulldown: get pulldown status
 * @set_pulldown: enable/disable pulldown
 * @get_schmitt_trig: get schmitt trigger status
 * @disable_schmitt_trig: disable schmitt trigger
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 * @irq_type: return irq type
 */
struct at91_pinctrl_mux_ops {
	enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
	void (*mux_A_periph)(void __iomem *pio, unsigned mask);
	void (*mux_B_periph)(void __iomem *pio, unsigned mask);
	void (*mux_C_periph)(void __iomem *pio, unsigned mask);
	void (*mux_D_periph)(void __iomem *pio, unsigned mask);
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	bool (*get_deglitch)(void __iomem *pio, unsigned pin);
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	void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
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	bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
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	void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
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	bool (*get_pulldown)(void __iomem *pio, unsigned pin);
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	void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
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	bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
	void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
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	unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
	void (*set_drivestrength)(void __iomem *pio, unsigned pin,
					u32 strength);
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	/* irq */
	int (*irq_type)(struct irq_data *d, unsigned type);
};

static int gpio_irq_type(struct irq_data *d, unsigned type);
static int alt_gpio_irq_type(struct irq_data *d, unsigned type);

struct at91_pinctrl {
	struct device		*dev;
	struct pinctrl_dev	*pctl;

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	int			nactive_banks;
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	uint32_t		*mux_mask;
	int			nmux;

	struct at91_pmx_func	*functions;
	int			nfunctions;

	struct at91_pin_group	*groups;
	int			ngroups;

	struct at91_pinctrl_mux_ops *ops;
};

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static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
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				const struct at91_pinctrl *info,
				const char *name)
{
	const struct at91_pin_group *grp = NULL;
	int i;

	for (i = 0; i < info->ngroups; i++) {
		if (strcmp(info->groups[i].name, name))
			continue;

		grp = &info->groups[i];
		dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
		break;
	}

	return grp;
}

static int at91_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	return info->ngroups;
}

static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
				       unsigned selector)
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	return info->groups[selector].name;
}

static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
			       const unsigned **pins,
			       unsigned *npins)
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	if (selector >= info->ngroups)
		return -EINVAL;

	*pins = info->groups[selector].pins;
	*npins = info->groups[selector].npins;

	return 0;
}

static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
		   unsigned offset)
{
	seq_printf(s, "%s", dev_name(pctldev->dev));
}

static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
			struct device_node *np,
			struct pinctrl_map **map, unsigned *num_maps)
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	const struct at91_pin_group *grp;
	struct pinctrl_map *new_map;
	struct device_node *parent;
	int map_num = 1;
	int i;

	/*
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	 * first find the group of this node and check if we need to create
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	 * config maps for pins
	 */
	grp = at91_pinctrl_find_group_by_name(info, np->name);
	if (!grp) {
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		dev_err(info->dev, "unable to find group for node %pOFn\n",
			np);
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		return -EINVAL;
	}

	map_num += grp->npins;
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	new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
			       GFP_KERNEL);
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	if (!new_map)
		return -ENOMEM;

	*map = new_map;
	*num_maps = map_num;

	/* create mux map */
	parent = of_get_parent(np);
	if (!parent) {
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		devm_kfree(pctldev->dev, new_map);
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		return -EINVAL;
	}
	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	new_map[0].data.mux.function = parent->name;
	new_map[0].data.mux.group = np->name;
	of_node_put(parent);

	/* create config map */
	new_map++;
	for (i = 0; i < grp->npins; i++) {
		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
		new_map[i].data.configs.group_or_pin =
				pin_get_name(pctldev, grp->pins[i]);
		new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
		new_map[i].data.configs.num_configs = 1;
	}

	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
		(*map)->data.mux.function, (*map)->data.mux.group, map_num);

	return 0;
}

static void at91_dt_free_map(struct pinctrl_dev *pctldev,
				struct pinctrl_map *map, unsigned num_maps)
{
}

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static const struct pinctrl_ops at91_pctrl_ops = {
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	.get_groups_count	= at91_get_groups_count,
	.get_group_name		= at91_get_group_name,
	.get_group_pins		= at91_get_group_pins,
	.pin_dbg_show		= at91_pin_dbg_show,
	.dt_node_to_map		= at91_dt_node_to_map,
	.dt_free_map		= at91_dt_free_map,
};

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static void __iomem *pin_to_controller(struct at91_pinctrl *info,
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				 unsigned int bank)
{
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	if (!gpio_chips[bank])
		return NULL;

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	return gpio_chips[bank]->regbase;
}

static inline int pin_to_bank(unsigned pin)
{
	return pin /= MAX_NB_GPIO_PER_BANK;
}

static unsigned pin_to_mask(unsigned int pin)
{
	return 1 << pin;
}

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static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
{
	/* return the shift value for a pin for "two bit" per pin registers,
	 * i.e. drive strength */
	return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
			? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
}

static unsigned sama5d3_get_drive_register(unsigned int pin)
{
	/* drive strength is split between two registers
	 * with two bits per pin */
	return (pin >= MAX_NB_GPIO_PER_BANK/2)
			? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
}

static unsigned at91sam9x5_get_drive_register(unsigned int pin)
{
	/* drive strength is split between two registers
	 * with two bits per pin */
	return (pin >= MAX_NB_GPIO_PER_BANK/2)
			? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
}

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static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
{
	writel_relaxed(mask, pio + PIO_IDR);
}

static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
{
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	return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
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}

static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
{
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	if (on)
		writel_relaxed(mask, pio + PIO_PPDDR);

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	writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
}

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static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
{
	*val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
	return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
}

static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
				bool is_on, bool val)
{
	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
	writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
}

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static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
{
	return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
}

static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
{
	writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
}

static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
{
	writel_relaxed(mask, pio + PIO_ASR);
}

static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
{
	writel_relaxed(mask, pio + PIO_BSR);
}

static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
{

	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
						pio + PIO_ABCDSR1);
	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
						pio + PIO_ABCDSR2);
}

static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
{
	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
						pio + PIO_ABCDSR1);
	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
						pio + PIO_ABCDSR2);
}

static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
{
	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
}

static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
{
	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
}

static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
{
	unsigned select;

	if (readl_relaxed(pio + PIO_PSR) & mask)
		return AT91_MUX_GPIO;

	select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
	select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);

	return select + 1;
}

static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
{
	unsigned select;

	if (readl_relaxed(pio + PIO_PSR) & mask)
		return AT91_MUX_GPIO;

	select = readl_relaxed(pio + PIO_ABSR) & mask;

	return select + 1;
}

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static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
{
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	return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
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}

static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
{
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	writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
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}

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static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
{
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	if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
		return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
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	return false;
}

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static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
{
	if (is_on)
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		writel_relaxed(mask, pio + PIO_IFSCDR);
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	at91_mux_set_deglitch(pio, mask, is_on);
}

static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
{
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	*div = readl_relaxed(pio + PIO_SCDR);
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	return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
	       ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
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}

static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
				bool is_on, u32 div)
{
	if (is_on) {
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		writel_relaxed(mask, pio + PIO_IFSCER);
		writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
		writel_relaxed(mask, pio + PIO_IFER);
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	} else
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		writel_relaxed(mask, pio + PIO_IFSCDR);
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}

static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
{
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	return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
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}

static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
{
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	if (is_on)
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		writel_relaxed(mask, pio + PIO_PUDR);
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	writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
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}

static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
{
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	writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
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}

static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
{
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	return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
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}

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static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
{
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	unsigned tmp = readl_relaxed(reg);
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	tmp = tmp >> two_bit_pin_value_shift_amount(pin);

	return tmp & DRIVE_STRENGTH_MASK;
}

static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
							unsigned pin)
{
	unsigned tmp = read_drive_strength(pio +
					sama5d3_get_drive_register(pin), pin);

	/* SAMA5 strength is 1:1 with our defines,
	 * except 0 is equivalent to low per datasheet */
	if (!tmp)
		tmp = DRIVE_STRENGTH_LOW;

	return tmp;
}

static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
							unsigned pin)
{
	unsigned tmp = read_drive_strength(pio +
				at91sam9x5_get_drive_register(pin), pin);

	/* strength is inverse in SAM9x5s hardware with the pinctrl defines
	 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
	tmp = DRIVE_STRENGTH_HI - tmp;

	return tmp;
}

static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
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	unsigned tmp = readl_relaxed(reg);
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	unsigned shift = two_bit_pin_value_shift_amount(pin);

	tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
	tmp |= strength << shift;

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	writel_relaxed(tmp, reg);
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}

static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
						u32 setting)
{
	/* do nothing if setting is zero */
	if (!setting)
		return;

	/* strength is 1 to 1 with setting for SAMA5 */
	set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
}

static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
						u32 setting)
{
	/* do nothing if setting is zero */
	if (!setting)
		return;

	/* strength is inverse on SAM9x5s with our defines
	 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
	setting = DRIVE_STRENGTH_HI - setting;

	set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
				setting);
}

609 610 611 612
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
	.get_periph	= at91_mux_get_periph,
	.mux_A_periph	= at91_mux_set_A_periph,
	.mux_B_periph	= at91_mux_set_B_periph,
613 614
	.get_deglitch	= at91_mux_get_deglitch,
	.set_deglitch	= at91_mux_set_deglitch,
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	.irq_type	= gpio_irq_type,
};

static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
	.get_periph	= at91_mux_pio3_get_periph,
	.mux_A_periph	= at91_mux_pio3_set_A_periph,
	.mux_B_periph	= at91_mux_pio3_set_B_periph,
	.mux_C_periph	= at91_mux_pio3_set_C_periph,
	.mux_D_periph	= at91_mux_pio3_set_D_periph,
624
	.get_deglitch	= at91_mux_pio3_get_deglitch,
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	.set_deglitch	= at91_mux_pio3_set_deglitch,
	.get_debounce	= at91_mux_pio3_get_debounce,
	.set_debounce	= at91_mux_pio3_set_debounce,
	.get_pulldown	= at91_mux_pio3_get_pulldown,
	.set_pulldown	= at91_mux_pio3_set_pulldown,
	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
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	.get_drivestrength = at91_mux_sam9x5_get_drivestrength,
	.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
	.irq_type	= alt_gpio_irq_type,
};

static struct at91_pinctrl_mux_ops sama5d3_ops = {
	.get_periph	= at91_mux_pio3_get_periph,
	.mux_A_periph	= at91_mux_pio3_set_A_periph,
	.mux_B_periph	= at91_mux_pio3_set_B_periph,
	.mux_C_periph	= at91_mux_pio3_set_C_periph,
	.mux_D_periph	= at91_mux_pio3_set_D_periph,
	.get_deglitch	= at91_mux_pio3_get_deglitch,
	.set_deglitch	= at91_mux_pio3_set_deglitch,
	.get_debounce	= at91_mux_pio3_get_debounce,
	.set_debounce	= at91_mux_pio3_set_debounce,
	.get_pulldown	= at91_mux_pio3_get_pulldown,
	.set_pulldown	= at91_mux_pio3_set_pulldown,
	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
	.get_drivestrength = at91_mux_sama5d3_get_drivestrength,
	.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
653 654 655 656 657 658
	.irq_type	= alt_gpio_irq_type,
};

static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
{
	if (pin->mux) {
659
		dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
660 661
			pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
	} else {
662
		dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
663 664 665 666
			pin->bank + 'A', pin->pin, pin->conf);
	}
}

667
static int pin_check_config(struct at91_pinctrl *info, const char *name,
668 669 670 671 672
			    int index, const struct at91_pmx_pin *pin)
{
	int mux;

	/* check if it's a valid config */
673
	if (pin->bank >= gpio_banks) {
674
		dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
675
			name, index, pin->bank, gpio_banks);
676 677 678
		return -EINVAL;
	}

679 680 681 682 683 684
	if (!gpio_chips[pin->bank]) {
		dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
			name, index, pin->bank);
		return -ENXIO;
	}

685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721
	if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
		dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
			name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
		return -EINVAL;
	}

	if (!pin->mux)
		return 0;

	mux = pin->mux - 1;

	if (mux >= info->nmux) {
		dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
			name, index, mux, info->nmux);
		return -EINVAL;
	}

	if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
		dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
			name, index, mux, pin->bank + 'A', pin->pin);
		return -EINVAL;
	}

	return 0;
}

static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
{
	writel_relaxed(mask, pio + PIO_PDR);
}

static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
{
	writel_relaxed(mask, pio + PIO_PER);
	writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
}

722 723
static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
			unsigned group)
724 725 726 727 728 729 730 731 732 733 734 735 736
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
	const struct at91_pmx_pin *pin;
	uint32_t npins = info->groups[group].npins;
	int i, ret;
	unsigned mask;
	void __iomem *pio;

	dev_dbg(info->dev, "enable function %s group %s\n",
		info->functions[selector].name, info->groups[group].name);

	/* first check that all the pins of the group are valid with a valid
737
	 * parameter */
738 739 740 741 742 743 744 745 746 747 748
	for (i = 0; i < npins; i++) {
		pin = &pins_conf[i];
		ret = pin_check_config(info, info->groups[group].name, i, pin);
		if (ret)
			return ret;
	}

	for (i = 0; i < npins; i++) {
		pin = &pins_conf[i];
		at91_pin_dbg(info->dev, pin);
		pio = pin_to_controller(info, pin->bank);
749 750 751 752

		if (!pio)
			continue;

753 754
		mask = pin_to_mask(pin->pin);
		at91_mux_disable_interrupt(pio, mask);
755
		switch (pin->mux) {
756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
		case AT91_MUX_GPIO:
			at91_mux_gpio_enable(pio, mask, 1);
			break;
		case AT91_MUX_PERIPH_A:
			info->ops->mux_A_periph(pio, mask);
			break;
		case AT91_MUX_PERIPH_B:
			info->ops->mux_B_periph(pio, mask);
			break;
		case AT91_MUX_PERIPH_C:
			if (!info->ops->mux_C_periph)
				return -EINVAL;
			info->ops->mux_C_periph(pio, mask);
			break;
		case AT91_MUX_PERIPH_D:
			if (!info->ops->mux_D_periph)
				return -EINVAL;
			info->ops->mux_D_periph(pio, mask);
			break;
		}
		if (pin->mux)
			at91_mux_gpio_disable(pio, mask);
	}

	return 0;
}

static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	return info->nfunctions;
}

static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
					  unsigned selector)
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	return info->functions[selector].name;
}

static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
			       const char * const **groups,
			       unsigned * const num_groups)
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	*groups = info->functions[selector].groups;
	*num_groups = info->functions[selector].ngroups;

	return 0;
}

810 811 812
static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
				    struct pinctrl_gpio_range *range,
				    unsigned offset)
813 814 815 816 817 818 819 820 821 822 823 824 825 826 827
{
	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	struct at91_gpio_chip *at91_chip;
	struct gpio_chip *chip;
	unsigned mask;

	if (!range) {
		dev_err(npct->dev, "invalid range\n");
		return -EINVAL;
	}
	if (!range->gc) {
		dev_err(npct->dev, "missing GPIO chip in range\n");
		return -EINVAL;
	}
	chip = range->gc;
828
	at91_chip = gpiochip_get_data(chip);
829 830 831 832 833 834 835 836 837 838 839 840 841

	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);

	mask = 1 << (offset - chip->base);

	dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
		offset, 'A' + range->id, offset - chip->base, mask);

	writel_relaxed(mask, at91_chip->regbase + PIO_PER);

	return 0;
}

842 843 844
static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
				   struct pinctrl_gpio_range *range,
				   unsigned offset)
845 846 847 848 849 850 851
{
	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
	/* Set the pin to some default state, GPIO is usually default */
}

852
static const struct pinmux_ops at91_pmx_ops = {
853 854 855
	.get_functions_count	= at91_pmx_get_funcs_count,
	.get_function_name	= at91_pmx_get_func_name,
	.get_function_groups	= at91_pmx_get_groups,
856
	.set_mux		= at91_pmx_set,
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	.gpio_request_enable	= at91_gpio_request_enable,
	.gpio_disable_free	= at91_gpio_disable_free,
};

static int at91_pinconf_get(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long *config)
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	void __iomem *pio;
	unsigned pin;
867
	int div;
868
	bool out;
869

870 871
	*config = 0;
	dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
872
	pio = pin_to_controller(info, pin_to_bank(pin_id));
873 874 875 876

	if (!pio)
		return -EINVAL;

877 878 879 880 881 882 883 884
	pin = pin_id % MAX_NB_GPIO_PER_BANK;

	if (at91_mux_get_multidrive(pio, pin))
		*config |= MULTI_DRIVE;

	if (at91_mux_get_pullup(pio, pin))
		*config |= PULL_UP;

885 886 887 888 889 890 891 892
	if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
		*config |= DEGLITCH;
	if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
		*config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
	if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
		*config |= PULL_DOWN;
	if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
		*config |= DIS_SCHMIT;
893 894 895
	if (info->ops->get_drivestrength)
		*config |= (info->ops->get_drivestrength(pio, pin)
				<< DRIVE_STRENGTH_SHIFT);
896 897
	if (at91_mux_get_output(pio, pin, &out))
		*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
898

899 900 901 902
	return 0;
}

static int at91_pinconf_set(struct pinctrl_dev *pctldev,
903 904
			     unsigned pin_id, unsigned long *configs,
			     unsigned num_configs)
905 906 907 908
{
	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	unsigned mask;
	void __iomem *pio;
909 910
	int i;
	unsigned long config;
911
	unsigned pin;
912 913 914 915 916 917 918 919

	for (i = 0; i < num_configs; i++) {
		config = configs[i];

		dev_dbg(info->dev,
			"%s:%d, pin_id=%d, config=0x%lx",
			__func__, __LINE__, pin_id, config);
		pio = pin_to_controller(info, pin_to_bank(pin_id));
920 921 922 923

		if (!pio)
			return -EINVAL;

924 925
		pin = pin_id % MAX_NB_GPIO_PER_BANK;
		mask = pin_to_mask(pin);
926 927 928 929

		if (config & PULL_UP && config & PULL_DOWN)
			return -EINVAL;

930 931
		at91_mux_set_output(pio, mask, config & OUTPUT,
				    (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
932 933 934 935 936 937
		at91_mux_set_pullup(pio, mask, config & PULL_UP);
		at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
		if (info->ops->set_deglitch)
			info->ops->set_deglitch(pio, mask, config & DEGLITCH);
		if (info->ops->set_debounce)
			info->ops->set_debounce(pio, mask, config & DEBOUNCE,
938
				(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
939 940 941 942
		if (info->ops->set_pulldown)
			info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
		if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
			info->ops->disable_schmitt_trig(pio, mask);
943 944 945 946
		if (info->ops->set_drivestrength)
			info->ops->set_drivestrength(pio, pin,
				(config & DRIVE_STRENGTH)
					>> DRIVE_STRENGTH_SHIFT);
947 948

	} /* for each config */
949

950 951 952
	return 0;
}

953 954 955 956 957 958 959 960 961
#define DBG_SHOW_FLAG(flag) do {		\
	if (config & flag) {			\
		if (num_conf)			\
			seq_puts(s, "|");	\
		seq_puts(s, #flag);		\
		num_conf++;			\
	}					\
} while (0)

962 963 964 965 966 967 968 969 970
#define DBG_SHOW_FLAG_MASKED(mask,flag) do {	\
	if ((config & mask) == flag) {		\
		if (num_conf)			\
			seq_puts(s, "|");	\
		seq_puts(s, #flag);		\
		num_conf++;			\
	}					\
} while (0)

971 972 973
static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
				   struct seq_file *s, unsigned pin_id)
{
974
	unsigned long config;
975
	int val, num_conf = 0;
976

977
	at91_pinconf_get(pctldev, pin_id, &config);
978 979 980 981 982 983

	DBG_SHOW_FLAG(MULTI_DRIVE);
	DBG_SHOW_FLAG(PULL_UP);
	DBG_SHOW_FLAG(PULL_DOWN);
	DBG_SHOW_FLAG(DIS_SCHMIT);
	DBG_SHOW_FLAG(DEGLITCH);
984 985 986
	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
987 988 989 990 991
	DBG_SHOW_FLAG(DEBOUNCE);
	if (config & DEBOUNCE) {
		val = config >> DEBOUNCE_VAL_SHIFT;
		seq_printf(s, "(%d)", val);
	}
992

993
	return;
994 995 996 997 998 999 1000
}

static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
					 struct seq_file *s, unsigned group)
{
}

1001
static const struct pinconf_ops at91_pinconf_ops = {
1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016
	.pin_config_get			= at91_pinconf_get,
	.pin_config_set			= at91_pinconf_set,
	.pin_config_dbg_show		= at91_pinconf_dbg_show,
	.pin_config_group_dbg_show	= at91_pinconf_group_dbg_show,
};

static struct pinctrl_desc at91_pinctrl_desc = {
	.pctlops	= &at91_pctrl_ops,
	.pmxops		= &at91_pmx_ops,
	.confops	= &at91_pinconf_ops,
	.owner		= THIS_MODULE,
};

static const char *gpio_compat = "atmel,at91rm9200-gpio";

1017 1018
static void at91_pinctrl_child_count(struct at91_pinctrl *info,
				     struct device_node *np)
1019 1020 1021 1022 1023
{
	struct device_node *child;

	for_each_child_of_node(np, child) {
		if (of_device_is_compatible(child, gpio_compat)) {
1024 1025
			if (of_device_is_available(child))
				info->nactive_banks++;
1026 1027 1028 1029 1030 1031 1032
		} else {
			info->nfunctions++;
			info->ngroups += of_get_child_count(child);
		}
	}
}

1033 1034
static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
				 struct device_node *np)
1035 1036 1037
{
	int ret = 0;
	int size;
1038
	const __be32 *list;
1039 1040 1041 1042 1043 1044 1045 1046

	list = of_get_property(np, "atmel,mux-mask", &size);
	if (!list) {
		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
		return -EINVAL;
	}

	size /= sizeof(*list);
1047 1048
	if (!size || size % gpio_banks) {
		dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1049 1050
		return -EINVAL;
	}
1051
	info->nmux = size / gpio_banks;
1052

1053 1054
	info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
				      GFP_KERNEL);
1055
	if (!info->mux_mask)
1056 1057 1058 1059 1060 1061 1062 1063 1064
		return -ENOMEM;

	ret = of_property_read_u32_array(np, "atmel,mux-mask",
					  info->mux_mask, size);
	if (ret)
		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
	return ret;
}

1065 1066 1067
static int at91_pinctrl_parse_groups(struct device_node *np,
				     struct at91_pin_group *grp,
				     struct at91_pinctrl *info, u32 index)
1068 1069 1070
{
	struct at91_pmx_pin *pin;
	int size;
1071
	const __be32 *list;
1072 1073
	int i, j;

1074
	dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091

	/* Initialise group */
	grp->name = np->name;

	/*
	 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
	 * do sanity check and calculate pins number
	 */
	list = of_get_property(np, "atmel,pins", &size);
	/* we do not check return since it's safe node passed down */
	size /= sizeof(*list);
	if (!size || size % 4) {
		dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
		return -EINVAL;
	}

	grp->npins = size / 4;
1092 1093 1094 1095 1096 1097
	pin = grp->pins_conf = devm_kcalloc(info->dev,
					    grp->npins,
					    sizeof(struct at91_pmx_pin),
					    GFP_KERNEL);
	grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
				 GFP_KERNEL);
1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114
	if (!grp->pins_conf || !grp->pins)
		return -ENOMEM;

	for (i = 0, j = 0; i < size; i += 4, j++) {
		pin->bank = be32_to_cpu(*list++);
		pin->pin = be32_to_cpu(*list++);
		grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
		pin->mux = be32_to_cpu(*list++);
		pin->conf = be32_to_cpu(*list++);

		at91_pin_dbg(info->dev, pin);
		pin++;
	}

	return 0;
}

1115 1116
static int at91_pinctrl_parse_functions(struct device_node *np,
					struct at91_pinctrl *info, u32 index)
1117 1118 1119 1120 1121 1122 1123 1124
{
	struct device_node *child;
	struct at91_pmx_func *func;
	struct at91_pin_group *grp;
	int ret;
	static u32 grp_index;
	u32 i = 0;

1125
	dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1126 1127 1128 1129 1130 1131

	func = &info->functions[index];

	/* Initialise function */
	func->name = np->name;
	func->ngroups = of_get_child_count(np);
1132
	if (func->ngroups == 0) {
1133 1134 1135
		dev_err(info->dev, "no groups defined\n");
		return -EINVAL;
	}
1136 1137
	func->groups = devm_kcalloc(info->dev,
			func->ngroups, sizeof(char *), GFP_KERNEL);
1138 1139 1140 1141 1142 1143 1144
	if (!func->groups)
		return -ENOMEM;

	for_each_child_of_node(np, child) {
		func->groups[i] = child->name;
		grp = &info->groups[grp_index++];
		ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1145 1146
		if (ret) {
			of_node_put(child);
1147
			return ret;
1148
		}
1149 1150 1151 1152 1153
	}

	return 0;
}

1154
static const struct of_device_id at91_pinctrl_of_match[] = {
1155
	{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1156 1157 1158 1159 1160
	{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
	{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
	{ /* sentinel */ }
};

1161 1162
static int at91_pinctrl_probe_dt(struct platform_device *pdev,
				 struct at91_pinctrl *info)
1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173
{
	int ret = 0;
	int i, j;
	uint32_t *tmp;
	struct device_node *np = pdev->dev.of_node;
	struct device_node *child;

	if (!np)
		return -ENODEV;

	info->dev = &pdev->dev;
1174
	info->ops = (struct at91_pinctrl_mux_ops *)
1175 1176 1177
		of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
	at91_pinctrl_child_count(info, np);

1178
	if (gpio_banks < 1) {
1179
		dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190
		return -EINVAL;
	}

	ret = at91_pinctrl_mux_mask(info, np);
	if (ret)
		return ret;

	dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);

	dev_dbg(&pdev->dev, "mux-mask\n");
	tmp = info->mux_mask;
1191
	for (i = 0; i < gpio_banks; i++) {
1192 1193 1194 1195 1196 1197 1198
		for (j = 0; j < info->nmux; j++, tmp++) {
			dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
		}
	}

	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1199 1200 1201
	info->functions = devm_kcalloc(&pdev->dev,
					info->nfunctions,
					sizeof(struct at91_pmx_func),
1202 1203 1204 1205
					GFP_KERNEL);
	if (!info->functions)
		return -ENOMEM;

1206 1207 1208
	info->groups = devm_kcalloc(&pdev->dev,
					info->ngroups,
					sizeof(struct at91_pin_group),
1209 1210 1211 1212
					GFP_KERNEL);
	if (!info->groups)
		return -ENOMEM;

1213
	dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224
	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);

	i = 0;

	for_each_child_of_node(np, child) {
		if (of_device_is_compatible(child, gpio_compat))
			continue;
		ret = at91_pinctrl_parse_functions(child, info, i++);
		if (ret) {
			dev_err(&pdev->dev, "failed to parse function\n");
1225
			of_node_put(child);
1226 1227 1228 1229 1230 1231 1232
			return ret;
		}
	}

	return 0;
}

1233
static int at91_pinctrl_probe(struct platform_device *pdev)
1234 1235 1236
{
	struct at91_pinctrl *info;
	struct pinctrl_pin_desc *pdesc;
1237
	int ret, i, j, k, ngpio_chips_enabled = 0;
1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251

	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
	if (!info)
		return -ENOMEM;

	ret = at91_pinctrl_probe_dt(pdev, info);
	if (ret)
		return ret;

	/*
	 * We need all the GPIO drivers to probe FIRST, or we will not be able
	 * to obtain references to the struct gpio_chip * for them, and we
	 * need this to proceed.
	 */
1252 1253 1254 1255 1256 1257 1258 1259 1260 1261
	for (i = 0; i < gpio_banks; i++)
		if (gpio_chips[i])
			ngpio_chips_enabled++;

	if (ngpio_chips_enabled < info->nactive_banks) {
		dev_warn(&pdev->dev,
			 "All GPIO chips are not registered yet (%d/%d)\n",
			 ngpio_chips_enabled, info->nactive_banks);
		devm_kfree(&pdev->dev, info);
		return -EPROBE_DEFER;
1262 1263 1264
	}

	at91_pinctrl_desc.name = dev_name(&pdev->dev);
1265
	at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1266
	at91_pinctrl_desc.pins = pdesc =
1267 1268 1269
		devm_kcalloc(&pdev->dev,
			     at91_pinctrl_desc.npins, sizeof(*pdesc),
			     GFP_KERNEL);
1270 1271 1272 1273

	if (!at91_pinctrl_desc.pins)
		return -ENOMEM;

1274
	for (i = 0, k = 0; i < gpio_banks; i++) {
1275 1276 1277 1278 1279 1280 1281 1282
		for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
			pdesc->number = k;
			pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
			pdesc++;
		}
	}

	platform_set_drvdata(pdev, info);
1283 1284
	info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
					   info);
1285

1286
	if (IS_ERR(info->pctl)) {
1287
		dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1288
		return PTR_ERR(info->pctl);
1289 1290 1291
	}

	/* We will handle a range of GPIO pins */
1292 1293 1294
	for (i = 0; i < gpio_banks; i++)
		if (gpio_chips[i])
			pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1295 1296 1297 1298 1299 1300

	dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");

	return 0;
}

1301 1302
static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
1303
	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1304 1305 1306 1307 1308 1309 1310 1311
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;
	u32 osr;

	osr = readl_relaxed(pio + PIO_OSR);
	return !(osr & mask);
}

1312 1313
static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
1314
	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1315 1316 1317 1318 1319 1320 1321 1322 1323
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;

	writel_relaxed(mask, pio + PIO_ODR);
	return 0;
}

static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
{
1324
	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;
	u32 pdsr;

	pdsr = readl_relaxed(pio + PIO_PDSR);
	return (pdsr & mask) != 0;
}

static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
				int val)
{
1336
	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1337 1338 1339 1340 1341 1342
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;

	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
}

1343 1344 1345
static void at91_gpio_set_multiple(struct gpio_chip *chip,
				      unsigned long *mask, unsigned long *bits)
{
1346
	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357
	void __iomem *pio = at91_gpio->regbase;

#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
	/* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
	uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
	uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);

	writel_relaxed(set_mask, pio + PIO_SODR);
	writel_relaxed(clear_mask, pio + PIO_CODR);
}

1358 1359 1360
static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
				int val)
{
1361
	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;

	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
	writel_relaxed(mask, pio + PIO_OER);

	return 0;
}

#ifdef CONFIG_DEBUG_FS
static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	enum at91_mux mode;
	int i;
1376
	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1377 1378 1379
	void __iomem *pio = at91_gpio->regbase;

	for (i = 0; i < chip->ngpio; i++) {
1380
		unsigned mask = pin_to_mask(i);
1381 1382 1383 1384 1385 1386 1387 1388 1389
		const char *gpio_label;

		gpio_label = gpiochip_is_requested(chip, i);
		if (!gpio_label)
			continue;
		mode = at91_gpio->ops->get_periph(pio, mask);
		seq_printf(s, "[%s] GPIO%s%d: ",
			   gpio_label, chip->label, i);
		if (mode == AT91_MUX_GPIO) {
1390 1391 1392 1393 1394 1395 1396
			seq_printf(s, "[gpio] ");
			seq_printf(s, "%s ",
				      readl_relaxed(pio + PIO_OSR) & mask ?
				      "output" : "input");
			seq_printf(s, "%s\n",
				      readl_relaxed(pio + PIO_PDSR) & mask ?
				      "set" : "clear");
1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460
		} else {
			seq_printf(s, "[periph %c]\n",
				   mode + 'A' - 1);
		}
	}
}
#else
#define at91_gpio_dbg_show	NULL
#endif

/* Several AIC controller irqs are dispatched through this GPIO handler.
 * To use any AT91_PIN_* as an externally triggered IRQ, first call
 * at91_set_gpio_input() then maybe enable its glitch filter.
 * Then just request_irq() with the pin ID; it works like any ARM IRQ
 * handler.
 * First implementation always triggers on rising and falling edges
 * whereas the newer PIO3 can be additionally configured to trigger on
 * level, edge with any polarity.
 *
 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 * configuring them with at91_set_a_periph() or at91_set_b_periph().
 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
 */

static void gpio_irq_mask(struct irq_data *d)
{
	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
	void __iomem	*pio = at91_gpio->regbase;
	unsigned	mask = 1 << d->hwirq;

	if (pio)
		writel_relaxed(mask, pio + PIO_IDR);
}

static void gpio_irq_unmask(struct irq_data *d)
{
	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
	void __iomem	*pio = at91_gpio->regbase;
	unsigned	mask = 1 << d->hwirq;

	if (pio)
		writel_relaxed(mask, pio + PIO_IER);
}

static int gpio_irq_type(struct irq_data *d, unsigned type)
{
	switch (type) {
	case IRQ_TYPE_NONE:
	case IRQ_TYPE_EDGE_BOTH:
		return 0;
	default:
		return -EINVAL;
	}
}

/* Alternate irq type for PIO3 support */
static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
{
	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
	void __iomem	*pio = at91_gpio->regbase;
	unsigned	mask = 1 << d->hwirq;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
1461
		irq_set_handler_locked(d, handle_simple_irq);
1462 1463 1464 1465
		writel_relaxed(mask, pio + PIO_ESR);
		writel_relaxed(mask, pio + PIO_REHLSR);
		break;
	case IRQ_TYPE_EDGE_FALLING:
1466
		irq_set_handler_locked(d, handle_simple_irq);
1467 1468 1469 1470
		writel_relaxed(mask, pio + PIO_ESR);
		writel_relaxed(mask, pio + PIO_FELLSR);
		break;
	case IRQ_TYPE_LEVEL_LOW:
1471
		irq_set_handler_locked(d, handle_level_irq);
1472 1473 1474 1475
		writel_relaxed(mask, pio + PIO_LSR);
		writel_relaxed(mask, pio + PIO_FELLSR);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
1476
		irq_set_handler_locked(d, handle_level_irq);
1477 1478 1479 1480 1481 1482 1483 1484
		writel_relaxed(mask, pio + PIO_LSR);
		writel_relaxed(mask, pio + PIO_REHLSR);
		break;
	case IRQ_TYPE_EDGE_BOTH:
		/*
		 * disable additional interrupt modes:
		 * fall back to default behavior
		 */
1485
		irq_set_handler_locked(d, handle_simple_irq);
1486 1487 1488 1489
		writel_relaxed(mask, pio + PIO_AIMDR);
		return 0;
	case IRQ_TYPE_NONE:
	default:
1490
		pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1491 1492 1493 1494 1495 1496 1497 1498 1499
		return -EINVAL;
	}

	/* enable additional interrupt modes */
	writel_relaxed(mask, pio + PIO_AIMER);

	return 0;
}

1500 1501 1502 1503 1504
static void gpio_irq_ack(struct irq_data *d)
{
	/* the interrupt is already cleared before by reading ISR */
}

1505
#ifdef CONFIG_PM
1506 1507 1508 1509

static u32 wakeups[MAX_GPIO_BANKS];
static u32 backups[MAX_GPIO_BANKS];

1510 1511 1512 1513
static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
{
	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
	unsigned	bank = at91_gpio->pioc_idx;
1514
	unsigned mask = 1 << d->hwirq;
1515 1516 1517 1518

	if (unlikely(bank >= MAX_GPIO_BANKS))
		return -EINVAL;

1519 1520 1521 1522 1523
	if (state)
		wakeups[bank] |= mask;
	else
		wakeups[bank] &= ~mask;

1524 1525 1526 1527
	irq_set_irq_wake(at91_gpio->pioc_virq, state);

	return 0;
}
1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540

void at91_pinctrl_gpio_suspend(void)
{
	int i;

	for (i = 0; i < gpio_banks; i++) {
		void __iomem  *pio;

		if (!gpio_chips[i])
			continue;

		pio = gpio_chips[i]->regbase;

1541 1542 1543
		backups[i] = readl_relaxed(pio + PIO_IMR);
		writel_relaxed(backups[i], pio + PIO_IDR);
		writel_relaxed(wakeups[i], pio + PIO_IER);
1544

1545 1546 1547
		if (!wakeups[i])
			clk_disable_unprepare(gpio_chips[i]->clock);
		else
1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564
			printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
			       'A'+i, wakeups[i]);
	}
}

void at91_pinctrl_gpio_resume(void)
{
	int i;

	for (i = 0; i < gpio_banks; i++) {
		void __iomem  *pio;

		if (!gpio_chips[i])
			continue;

		pio = gpio_chips[i]->regbase;

1565 1566
		if (!wakeups[i])
			clk_prepare_enable(gpio_chips[i]->clock);
1567

1568 1569
		writel_relaxed(wakeups[i], pio + PIO_IDR);
		writel_relaxed(backups[i], pio + PIO_IER);
1570 1571 1572
	}
}

1573 1574
#else
#define gpio_irq_set_wake	NULL
1575
#endif /* CONFIG_PM */
1576

1577
static void gpio_irq_handler(struct irq_desc *desc)
1578
{
1579
	struct irq_chip *chip = irq_desc_get_chip(desc);
1580
	struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1581
	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1582 1583 1584 1585 1586 1587 1588
	void __iomem	*pio = at91_gpio->regbase;
	unsigned long	isr;
	int		n;

	chained_irq_enter(chip, desc);
	for (;;) {
		/* Reading ISR acks pending (edge triggered) GPIO interrupts.
1589
		 * When there are none pending, we're finished unless we need
1590 1591 1592 1593 1594 1595 1596 1597
		 * to process multiple banks (like ID_PIOCDE on sam9263).
		 */
		isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
		if (!isr) {
			if (!at91_gpio->next)
				break;
			at91_gpio = at91_gpio->next;
			pio = at91_gpio->regbase;
1598
			gpio_chip = &at91_gpio->chip;
1599 1600 1601
			continue;
		}

1602
		for_each_set_bit(n, &isr, BITS_PER_LONG) {
1603
			generic_handle_irq(irq_find_mapping(
1604
					   gpio_chip->irq.domain, n));
1605 1606 1607 1608 1609 1610
		}
	}
	chained_irq_exit(chip, desc);
	/* now it may re-trigger */
}

1611
static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1612 1613
				  struct at91_gpio_chip *at91_gpio)
{
1614
	struct gpio_chip	*gpiochip_prev = NULL;
1615
	struct at91_gpio_chip   *prev = NULL;
1616
	struct irq_data		*d = irq_get_irq_data(at91_gpio->pioc_virq);
1617
	struct irq_chip		*gpio_irqchip;
1618
	int ret, i;
1619

1620 1621 1622 1623
	gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL);
	if (!gpio_irqchip)
		return -ENOMEM;

1624 1625
	at91_gpio->pioc_hwirq = irqd_to_hwirq(d);

1626 1627 1628 1629 1630 1631 1632
	gpio_irqchip->name = "GPIO";
	gpio_irqchip->irq_ack = gpio_irq_ack;
	gpio_irqchip->irq_disable = gpio_irq_mask;
	gpio_irqchip->irq_mask = gpio_irq_mask;
	gpio_irqchip->irq_unmask = gpio_irq_unmask;
	gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
	gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1633 1634 1635 1636

	/* Disable irqs of this PIO controller */
	writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);

1637 1638 1639 1640 1641 1642
	/*
	 * Let the generic code handle this edge IRQ, the the chained
	 * handler will perform the actual work of handling the parent
	 * interrupt.
	 */
	ret = gpiochip_irqchip_add(&at91_gpio->chip,
1643
				   gpio_irqchip,
1644 1645
				   0,
				   handle_edge_irq,
1646
				   IRQ_TYPE_NONE);
1647 1648
	if (ret) {
		dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1649
			at91_gpio->pioc_idx);
1650 1651
		return ret;
	}
1652

1653 1654 1655 1656
	/* The top level handler handles one bank of GPIOs, except
	 * on some SoC it can handle up to three...
	 * We only set up the handler for the first of the list.
	 */
1657 1658 1659 1660
	gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
	if (!gpiochip_prev) {
		/* Then register the chain on the parent IRQ */
		gpiochip_set_chained_irqchip(&at91_gpio->chip,
1661
					     gpio_irqchip,
1662 1663
					     at91_gpio->pioc_virq,
					     gpio_irq_handler);
1664
		return 0;
1665
	}
1666

1667
	prev = gpiochip_get_data(gpiochip_prev);
1668

1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679
	/* we can only have 2 banks before */
	for (i = 0; i < 2; i++) {
		if (prev->next) {
			prev = prev->next;
		} else {
			prev->next = at91_gpio;
			return 0;
		}
	}

	return -EINVAL;
1680 1681 1682
}

/* This structure is replicated for each GPIO block allocated at probe time */
1683
static const struct gpio_chip at91_gpio_template = {
1684 1685
	.request		= gpiochip_generic_request,
	.free			= gpiochip_generic_free,
1686
	.get_direction		= at91_gpio_get_direction,
1687 1688 1689 1690
	.direction_input	= at91_gpio_direction_input,
	.get			= at91_gpio_get,
	.direction_output	= at91_gpio_direction_output,
	.set			= at91_gpio_set,
1691
	.set_multiple		= at91_gpio_set_multiple,
1692
	.dbg_show		= at91_gpio_dbg_show,
1693
	.can_sleep		= false,
1694 1695 1696
	.ngpio			= MAX_NB_GPIO_PER_BANK,
};

1697
static const struct of_device_id at91_gpio_of_match[] = {
1698 1699 1700 1701 1702
	{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
	{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
	{ /* sentinel */ }
};

1703
static int at91_gpio_probe(struct platform_device *pdev)
1704 1705 1706 1707 1708 1709 1710
{
	struct device_node *np = pdev->dev.of_node;
	struct resource *res;
	struct at91_gpio_chip *at91_chip = NULL;
	struct gpio_chip *chip;
	struct pinctrl_gpio_range *range;
	int ret = 0;
1711
	int irq, i;
1712 1713
	int alias_idx = of_alias_get_id(np, "gpio");
	uint32_t ngpio;
1714
	char **names;
1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733

	BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
	if (gpio_chips[alias_idx]) {
		ret = -EBUSY;
		goto err;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = irq;
		goto err;
	}

	at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
	if (!at91_chip) {
		ret = -ENOMEM;
		goto err;
	}

1734
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1735 1736 1737
	at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(at91_chip->regbase)) {
		ret = PTR_ERR(at91_chip->regbase);
1738 1739 1740
		goto err;
	}

1741
	at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1742 1743 1744 1745
		of_match_device(at91_gpio_of_match, &pdev->dev)->data;
	at91_chip->pioc_virq = irq;
	at91_chip->pioc_idx = alias_idx;

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