socfpga.c 2.86 KB
Newer Older
1
// SPDX-License-Identifier: GPL-2.0-or-later
2
/*
3
 *  Copyright (C) 2012-2015 Altera Corporation
4
 */
5
#include <linux/irqchip.h>
6
#include <linux/of_address.h>
7 8
#include <linux/of_irq.h>
#include <linux/of_platform.h>
9
#include <linux/reboot.h>
10
#include <linux/reset/socfpga.h>
11 12 13

#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
14
#include <asm/mach/map.h>
15
#include <asm/cacheflush.h>
16

17 18 19 20
#include "core.h"

void __iomem *sys_manager_base_addr;
void __iomem *rst_manager_base_addr;
21
void __iomem *sdr_ctl_base_addr;
22
unsigned long socfpga_cpu1start_addr;
23

24
static void __init socfpga_sysmgr_init(void)
25 26 27 28
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
29 30

	if (of_property_read_u32(np, "cpu1-start-addr",
31
			(u32 *) &socfpga_cpu1start_addr))
32 33
		pr_err("SMP: Need cpu1-start-addr in device tree.\n");

34 35 36 37
	/* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
	smp_wmb();
	sync_cache_w(&socfpga_cpu1start_addr);

38 39 40 41
	sys_manager_base_addr = of_iomap(np, 0);

	np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
	rst_manager_base_addr = of_iomap(np, 0);
42 43 44

	np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
	sdr_ctl_base_addr = of_iomap(np, 0);
45 46
}

47
static void __init socfpga_init_irq(void)
48
{
49
	irqchip_init();
50
	socfpga_sysmgr_init();
51 52
	if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
		socfpga_init_l2_ecc();
53 54 55

	if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
		socfpga_init_ocram_ecc();
56
	socfpga_reset_init();
57 58
}

59 60 61 62 63 64
static void __init socfpga_arria10_init_irq(void)
{
	irqchip_init();
	socfpga_sysmgr_init();
	if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
		socfpga_init_arria10_l2_ecc();
65 66
	if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
		socfpga_init_arria10_ocram_ecc();
67
	socfpga_reset_init();
68 69
}

70
static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
71
{
72 73 74 75
	u32 temp;

	temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);

76
	if (mode == REBOOT_HARD)
77 78 79 80
		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
	else
		temp |= RSTMGR_CTRL_SWWARMRSTREQ;
	writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
81 82
}

83 84 85 86 87 88 89 90 91 92 93 94 95
static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
{
	u32 temp;

	temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);

	if (mode == REBOOT_HARD)
		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
	else
		temp |= RSTMGR_CTRL_SWWARMRSTREQ;
	writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
}

96 97 98 99 100 101
static const char *altera_dt_match[] = {
	"altr,socfpga",
	NULL
};

DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
102 103
	.l2c_aux_val	= 0,
	.l2c_aux_mask	= ~0,
104
	.init_irq	= socfpga_init_irq,
105 106 107
	.restart	= socfpga_cyclone5_restart,
	.dt_compat	= altera_dt_match,
MACHINE_END
108 109 110 111 112 113 114 115 116

static const char *altera_a10_dt_match[] = {
	"altr,socfpga-arria10",
	NULL
};

DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
	.l2c_aux_val	= 0,
	.l2c_aux_mask	= ~0,
117
	.init_irq	= socfpga_arria10_init_irq,
118 119 120
	.restart	= socfpga_arria10_restart,
	.dt_compat	= altera_a10_dt_match,
MACHINE_END