Commit f38c02f3 authored by Thomas Gleixner's avatar Thomas Gleixner

arm: Fold irq_set_chip/irq_set_handler

Use irq_set_chip_and_handler() instead. Converted with coccinelle.
Signed-off-by: default avatarThomas Gleixner <[email protected]>
parent 9323f261
......@@ -319,8 +319,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
* Setup the Linux IRQ subsystem.
*/
for (i = irq_start; i < irq_limit; i++) {
irq_set_chip(i, &gic_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
irq_set_chip_data(i, gic);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
......
......@@ -88,8 +88,8 @@ void it8152_init_irq(void)
__raw_writel((0), IT8152_INTC_LDCNIRR);
for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
irq_set_chip(irq, &it8152_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &it8152_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
......
......@@ -203,8 +203,7 @@ static void locomo_setup_irq(struct locomo *lchip)
/* Install handlers for IRQ_LOCOMO_* */
for ( ; irq <= lchip->irq_base + 3; irq++) {
irq_set_chip(irq, &locomo_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
irq_set_chip_data(irq, lchip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
......
......@@ -472,15 +472,15 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
irq_set_chip(irq, &sa1111_low_chip);
irq_set_handler(irq, handle_edge_irq);
irq_set_chip_and_handler(irq, &sa1111_low_chip,
handle_edge_irq);
irq_set_chip_data(irq, sachip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
irq_set_chip(irq, &sa1111_high_chip);
irq_set_handler(irq, handle_edge_irq);
irq_set_chip_and_handler(irq, &sa1111_high_chip,
handle_edge_irq);
irq_set_chip_data(irq, sachip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
......
......@@ -305,8 +305,8 @@ static void __init vic_set_irq_sources(void __iomem *base,
if (vic_sources & (1 << i)) {
unsigned int irq = irq_start + i;
irq_set_chip(irq, &vic_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &vic_chip,
handle_level_irq);
irq_set_chip_data(irq, base);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
......
......@@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type)
*/
if (slot < 8) {
ec->irq = 32 + slot;
irq_set_chip(ec->irq, &ecard_chip);
irq_set_handler(ec->irq, handle_level_irq);
irq_set_chip_and_handler(ec->irq, &ecard_chip,
handle_level_irq);
set_irq_flags(ec->irq, IRQF_VALID);
}
......
......@@ -511,8 +511,8 @@ void __init at91_gpio_irq_setup(void)
* Can use the "simple" and not "edge" handler since it's
* shorter, and the AIC handles interrupts sanely.
*/
irq_set_chip(pin, &gpio_irqchip);
irq_set_handler(pin, handle_simple_irq);
irq_set_chip_and_handler(pin, &gpio_irqchip,
handle_simple_irq);
set_irq_flags(pin, IRQF_VALID);
}
......
......@@ -143,8 +143,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
/* Active Low interrupt, with the specified priority */
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
irq_set_chip(i, &at91_aic_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
......
......@@ -112,13 +112,13 @@ void __init clps711x_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
if (INT1_IRQS & (1 << i)) {
irq_set_handler(i, handle_level_irq);
irq_set_chip(i, &int1_chip);
irq_set_chip_and_handler(i, &int1_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
if (INT2_IRQS & (1 << i)) {
irq_set_handler(i, handle_level_irq);
irq_set_chip(i, &int2_chip);
irq_set_chip_and_handler(i, &int2_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}
......
......@@ -121,8 +121,7 @@ void __init dove_init_irq(void)
writel(0, PMU_INTERRUPT_CAUSE);
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
irq_set_chip(i, &pmu_irq_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
set_irq_flags(i, IRQF_VALID);
}
......
......@@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void)
local_irq_restore(flags);
for (irq = 0; irq < NR_IRQS; irq++) {
irq_set_chip(irq, &ebsa110_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
......
......@@ -231,8 +231,8 @@ void __init ep93xx_gpio_init_irq(void)
for (gpio_irq = gpio_to_irq(0);
gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
irq_set_chip(gpio_irq, &ep93xx_gpio_irq_chip);
irq_set_handler(gpio_irq, handle_level_irq);
irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
handle_level_irq);
set_irq_flags(gpio_irq, IRQF_VALID);
}
......
......@@ -119,8 +119,7 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+ MAX_IRQ_IN_COMBINER; i++) {
irq_set_chip(i, &combiner_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
irq_set_chip_data(i, &combiner_data[combiner_nr]);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
......
......@@ -208,8 +208,8 @@ int __init exynos4_init_irq_eint(void)
int irq;
for (irq = 0 ; irq <= 31 ; irq++) {
irq_set_chip(IRQ_EINT(irq), &exynos4_irq_eint);
irq_set_handler(IRQ_EINT(irq), handle_level_irq);
irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
handle_level_irq);
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
}
......
......@@ -102,8 +102,7 @@ static void __init __fb_init_irq(void)
*CSR_FIQ_DISABLE = -1;
for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
irq_set_chip(irq, &fb_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
......
......@@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq)
if (host_irq != (unsigned int)-1) {
for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
irq_set_chip(irq, &isa_lo_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &isa_lo_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
irq_set_chip(irq, &isa_hi_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &isa_hi_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
......
......@@ -217,8 +217,8 @@ void __init gemini_gpio_init(void)
for (j = GPIO_IRQ_BASE + i * 32;
j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
irq_set_chip(j, &gpio_irq_chip);
irq_set_handler(j, handle_edge_irq);
irq_set_chip_and_handler(j, &gpio_irq_chip,
handle_edge_irq);
set_irq_flags(j, IRQF_VALID);
}
......
......@@ -199,15 +199,15 @@ void __init h720x_init_irq (void)
/* Initialize global IRQ's, fast path */
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
irq_set_chip(irq, &h720x_global_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &h720x_global_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* Initialize multiplexed IRQ's, slow path */
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
irq_set_chip(irq, &h720x_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
......@@ -217,8 +217,8 @@ void __init h720x_init_irq (void)
#ifdef CONFIG_CPU_H7202
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
irq_set_chip(irq, &h720x_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
......
......@@ -202,8 +202,8 @@ void __init h7202_init_irq (void)
for (irq = IRQ_TIMER1;
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
__mask_timerx_irq(irq);
irq_set_chip(irq, &h7202_timerx_chip);
irq_set_handler(irq, handle_edge_irq);
irq_set_chip_and_handler(irq, &h7202_timerx_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
......
......@@ -68,8 +68,7 @@ void __init iop32x_init_irq(void)
*IOP3XX_PCIIRSR = 0x0f;
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip(i, &ext_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}
......@@ -110,9 +110,9 @@ void __init iop33x_init_irq(void)
*IOP3XX_PCIIRSR = 0x0f;
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip(i,
(i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i,
(i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}
......@@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void)
*/
for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
irq_set_chip(irq, &ixp2000_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
} else set_irq_flags(irq, 0);
}
......@@ -485,8 +485,8 @@ void __init ixp2000_init_irq(void)
for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
IXP2000_VALID_ERR_IRQ_MASK) {
irq_set_chip(irq, &ixp2000_err_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
else
......@@ -495,8 +495,8 @@ void __init ixp2000_init_irq(void)
irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
irq_set_chip(irq, &ixp2000_GPIO_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
......@@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void)
*/
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
irq_set_chip(irq, &ixp2000_pci_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}
......
......@@ -158,8 +158,8 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne
*board_irq_mask = 0xffffffff;
for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
irq_set_chip(irq, &ixdp2x00_cpld_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
......
......@@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void)
for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
if (irq & valid_irq_mask) {
irq_set_chip(irq, &ixdp2x01_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
} else {
set_irq_flags(irq, 0);
......
......@@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
{
switch (type) {
case IXP23XX_IRQ_LEVEL:
irq_set_chip(irq, &ixp23xx_irq_level_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
handle_level_irq);
break;
case IXP23XX_IRQ_EDGE:
irq_set_chip(irq, &ixp23xx_irq_edge_chip);
irq_set_handler(irq, handle_edge_irq);
irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
handle_edge_irq);
break;
}
set_irq_flags(irq, IRQF_VALID);
......@@ -324,8 +324,8 @@ void __init ixp23xx_init_irq(void)
}
for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
irq_set_chip(irq, &ixp23xx_pci_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
......
......@@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void)
irq++) {
if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
set_irq_flags(irq, IRQF_VALID);
irq_set_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixdp2351_inta_chip);
irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
handle_level_irq);
}
}
......@@ -147,8 +147,8 @@ void __init ixdp2351_init_irq(void)
irq++) {
if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
set_irq_flags(irq, IRQF_VALID);
irq_set_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixdp2351_intb_chip);
irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
handle_level_irq);
}
}
......
......@@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void)
/* Default to all level triggered */
for(i = 0; i < NR_IRQS; i++) {
irq_set_chip(i, &ixp4xx_irq_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
......
......@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
}
if (level_triggered) {
irq_set_chip(d->irq, &ks8695_irq_level_chip);
irq_set_handler(d->irq, handle_level_irq);
irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip,
handle_level_irq);
}
else {
irq_set_chip(d->irq, &ks8695_irq_edge_chip);
irq_set_handler(d->irq, handle_edge_irq);
irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip,
handle_edge_irq);
}
__raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
......@@ -158,16 +158,18 @@ void __init ks8695_init_irq(void)
case KS8695_IRQ_UART_RX:
case KS8695_IRQ_COMM_TX:
case KS8695_IRQ_COMM_RX:
irq_set_chip(irq, &ks8695_irq_level_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq,
&ks8695_irq_level_chip,
handle_level_irq);
break;
/* Edge-triggered interrupts */
default:
/* clear pending bit */
ks8695_irq_ack(irq_get_irq_data(irq));
irq_set_chip(irq, &ks8695_irq_edge_chip);
irq_set_handler(irq, handle_edge_irq);
irq_set_chip_and_handler(irq,
&ks8695_irq_edge_chip,
handle_edge_irq);
}
set_irq_flags(irq, IRQF_VALID);
......
......@@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void)
/* Configure supported IRQ's */
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip(i, &lpc32xx_irq_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
......
......@@ -48,8 +48,7 @@ void __init icu_init_irq(void)
for (irq = 0; irq < 64; irq++) {
icu_mask_irq(irq_get_irq_data(irq));
irq_set_chip(irq, &icu_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}
......@@ -214,8 +214,8 @@ int __init trout_init_gpio(void)
{
int i;
for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
irq_set_chip(i, &trout_gpio_irq_chip);
irq_set_handler(i, handle_edge_irq);
irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
......
......@@ -362,8 +362,8 @@ static int __devinit msm_gpio_probe(struct platform_device *dev)
for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
irq_set_chip(irq, &msm_gpio_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
......
......@@ -355,8 +355,8 @@ static int __init msm_init_gpio(void)
msm_gpio_chips[j].chip.ngpio)
j++;
irq_set_chip_data(i, &msm_gpio_chips[j]);
irq_set_chip(i, &msm_gpio_irq_chip);
irq_set_handler(i, handle_edge_irq);
irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
......
......@@ -357,8 +357,7 @@ void __init msm_init_irq(void)
writel(3, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) {
irq_set_chip(n, &msm_irq_chip);
irq_set_handler(n, handle_level_irq);
irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
set_irq_flags(n, IRQF_VALID);
}
}
......@@ -145,8 +145,7 @@ void __init msm_init_irq(void)
writel(1, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) {
irq_set_chip(n, &msm_irq_chip);
irq_set_handler(n, handle_level_irq);
irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
set_irq_flags(n, IRQF_VALID);
}
}
......@@ -158,8 +158,7 @@ void __init msm_init_sirc(void)
wake_enable = 0;
for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
irq_set_chip(i, &sirc_irq_chip);
irq_set_handler(i, handle_edge_irq);
irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
......
......@@ -199,8 +199,7 @@ static void __init mx31ads_init_expio(void)
__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
i++) {
irq_set_chip(i, &expio_irq_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
......
......@@ -265,8 +265,8 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
for (j = port[i].virtual_irq_start;
j < port[i].virtual_irq_start + 32; j++) {
irq_set_chip(j, &gpio_irq_chip);
irq_set_handler(j, handle_level_irq);
irq_set_chip_and_handler(j, &gpio_irq_chip,
handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
......
......@@ -74,8 +74,7 @@ void __init icoll_init_irq(void)
mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
irq_set_chip(i, &mxs_icoll_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
......@@ -171,8 +171,8 @@ void __init netx_init_irq(void)
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
irq_set_chip(irq, &netx_hif_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &netx_hif_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
......
......@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void)
__func__);
for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
irq_set_chip(i, &a9m9750dev_fpga_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
......
......@@ -67,8 +67,7 @@ void __init ns9xxx_init_irq(void)
__raw_writel(prio2irq(i), SYS_IVA(i));
for (i = 0; i <= 31; ++i) {
irq_set_chip(i, &ns9xxx_chip);
irq_set_handler(i, handle_fasteoi_irq);
irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq);
set_irq_flags(i, IRQF_VALID);
irq_set_status_flags(i, IRQ_LEVEL);
}
......
......@@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void)
__raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
irq_set_chip(irqno, &nuc93x_irq_chip);
irq_set_handler(irqno, handle_level_irq);
irq_set_chip_and_handler(irqno, &nuc93x_irq_chip,
handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
......@@ -230,8 +230,8 @@ void __init omap_init_irq(void)
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger);
irq_set_chip(j, &omap_irq_chip);
irq_set_handler(j, handle_level_irq);
irq_set_chip_and_handler(j, &omap_irq_chip,
handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
}
......
......@@ -223,8 +223,7 @@ void __init omap_init_irq(void)
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
for (i = 0; i < nr_of_irqs; i++) {
irq_set_chip(i, &omap_irq_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
......
......@@ -527,8 +527,8 @@ static void __init balloon3_init_irq(void)
pxa27x_init_irq();
/* setup extra Balloon3 irqs */
for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
irq_set_chip(irq, &balloon3_irq_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip_and_handler(irq, &balloon3_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
......
......@@ -137,8 +137,8 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
GEDR0 = 0x3;
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
irq_set_chip(irq, &pxa_low_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
handle_edge_irq);
irq_set_chip_data(irq<