Commit 60b95169 authored by Caz Yokoyama's avatar Caz Yokoyama Committed by Greg Kroah-Hartman

Revert "drm/i915/tgl: Add extra hdc flush workaround"

commit c09f6b4d0883dfb859c1ddcfb04c3260ef310ce0 upstream.

This reverts commit 36a6b5d9.

The commit takes care Wa_1604544889 which was fixed on a0 stepping based on
a0 replan. So no SW workaround is required on any stepping now.
Reviewed-by: default avatarMatt Roper <[email protected]>
Signed-off-by: default avatarCaz Yokoyama <[email protected]>
Signed-off-by: default avatarJosé Roberto de Souza <jose.so[email protected]>
Fixes: 36a6b5d9 ("drm/i915/tgl: Add extra hdc flush workaround")
Link: https://patchwork.freedesktop.org/patch/msgid/1c751[email protected]intel.com
(cherry picked from commit 175c4d9b3b9a60b4ea0b8cd034011808c6a03b05)
Signed-off-by: default avatarJani Nikula <[email protected]>
Signed-off-by: default avatarGreg Kroah-Hartman <[email protected]>
parent e086846a
......@@ -3503,26 +3503,6 @@ static int gen12_emit_flush_render(struct i915_request *request,
*cs++ = preparser_disable(false);
intel_ring_advance(request, cs);
/*
* Wa_1604544889:tgl
*/
if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
flags = 0;
flags |= PIPE_CONTROL_CS_STALL;
flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
flags |= PIPE_CONTROL_STORE_DATA_INDEX;
flags |= PIPE_CONTROL_QW_WRITE;
cs = intel_ring_begin(request, 6);
if (IS_ERR(cs))
return PTR_ERR(cs);
cs = gen8_emit_pipe_control(cs, flags,
LRC_PPHWSP_SCRATCH_ADDR);
intel_ring_advance(request, cs);
}
}
return 0;
......
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