Commit 5a9a8915 authored by Marc Zyngier's avatar Marc Zyngier Committed by Thomas Gleixner

irqchip/gic-v3-its: Add missing cache flushes

When the ITS is configured for non-cacheable transactions, make sure
that the allocated, zeroed memory is flushed to the Point of
Coherency, allowing the ITS to observe the zeros instead of random
garbage (or even get its own data overwritten by zeros being evicted
from the cache...).

Fixes: 241a386c "irqchip: gicv3-its: Use non-cacheable accesses when no shareability"
Reported-and-tested-by: default avatarStuart Yoder <[email protected]>
Signed-off-by: default avatarMarc Zyngier <[email protected]>
Cc: [email protected]
Cc: Pavel Fedin <[email protected]>
Cc: Jason Cooper <[email protected]>
Link:[email protected]Signed-off-by: default avatarThomas Gleixner <[email protected]>
parent 12e14066
......@@ -898,8 +898,10 @@ static int its_alloc_tables(const char *node_name, struct its_node *its)
* non-cacheable as well.
if (!shr)
if (!shr) {
cache = GITS_BASER_nC;
__flush_dcache_area(base, alloc_size);
goto retry_baser;
......@@ -1140,6 +1142,8 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
return NULL;
__flush_dcache_area(itt, sz);
dev->its = its;
dev->itt = itt;
dev->nr_ites = nr_ites;
Markdown is supported
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment