Commit 157add60 authored by Pavel Fedin's avatar Pavel Fedin Committed by Thomas Gleixner

irqchip/GICv2m: Fix GICv2m build warning on 32 bits

After GICv2m was enabled for 32-bit ARM kernel, a warning popped up:

drivers/irqchip/irq-gic-v2m.c: In function gicv2m_compose_msi_msg:
drivers/irqchip/irq-gic-v2m.c:100:2: warning: right shift count >= width
of type [enabled by default]
  msg->address_hi = (u32) (addr >> 32);

This patch fixes it by using proper macros for splitting up the value.
Signed-off-by: Pavel Fedin's avatarPavel Fedin <[email protected]>
Reviewed-by: default avatarMarc Zyngier <[email protected]>
Signed-off-by: default avatarMarc Zyngier <[email protected]>
Cc: [email protected]
Cc: Stuart Yoder <[email protected]>
Cc: Jason Cooper <[email protected]>
Link:[email protected]Signed-off-by: default avatarThomas Gleixner <[email protected]>
parent 5a9a8915
......@@ -95,8 +95,8 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
msg->address_hi = (u32) (addr >> 32);
msg->address_lo = (u32) (addr);
msg->address_hi = upper_32_bits(addr);
msg->address_lo = lower_32_bits(addr);
msg->data = data->hwirq;
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