• Will Deacon's avatar
    arm_pmu: Use disable_irq_nosync when disabling SPI in CPU teardown hook · b08e5fd9
    Will Deacon authored
    Commit 6de3f791 ("arm_pmu: explicitly enable/disable SPIs at hotplug")
    moved all of the arm_pmu IRQ enable/disable calls to the CPU hotplug hooks,
    regardless of whether they are implemented as PPIs or SPIs. This can
    lead to us sleeping from atomic context due to disable_irq blocking:
     | BUG: sleeping function called from invalid context at kernel/irq/manage.c:112
     | in_atomic(): 1, irqs_disabled(): 128, pid: 15, name: migration/1
     | no locks held by migration/1/15.
     | irq event stamp: 192
     | hardirqs last  enabled at (191): [<00000000803c2507>]
     | _raw_spin_unlock_irq+0x2c/0x4c
     | hardirqs last disabled at (192): [<000000007f57ad28>] multi_cpu_stop+0x9c/0x140
     | softirqs last  enabled at (0): [<0000000004ee1b58>]
     | copy_process.isra.77.part.78+0x43c/0x1504
     | softirqs last disabled at (0): [<          (null)>]           (null)
     | CPU: 1 PID: 15 Comm: migration/1 Not tainted 4.16.0-rc3-salvator-x #1651
     | Hardware name: Renesas Salvator-X board based on r8a7796 (DT)
     | Call trace:
     |  dump_backtrace+0x0/0x140
     |  show_stack+0x14/0x1c
     |  dump_stack+0xb4/0xf0
     |  ___might_sleep+0x1fc/0x218
     |  __might_sleep+0x70/0x80
     |  synchronize_irq+0x40/0xa8
     |  disable_irq+0x20/0x2c
     |  arm_perf_teardown_cpu+0x80/0xac
    Since the interrupt is always CPU-affine and this code is running with
    interrupts disabled, we can just use disable_irq_nosync as we know there
    isn't a concurrent invocation of the handler to worry about.
    Fixes: 6de3f791 ("arm_pmu: explicitly enable/disable SPIs at hotplug")
    Reported-by: default avatarGeert Uytterhoeven <[email protected]>
    Tested-by: default avatarGeert Uytterhoeven <[email protected]>
    Acked-by: default avatarMark Rutland <[email protected]>
    Signed-off-by: default avatarWill Deacon <[email protected]>
    Signed-off-by: default avatarCatalin Marinas <[email protected]>
arm_pmu.c 20.7 KB