megaraid_sas.h 58.1 KB
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/*
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 *  Linux MegaRAID driver for SAS based RAID controllers
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 *
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 *  Copyright (c) 2003-2013  LSI Corporation
 *  Copyright (c) 2013-2014  Avago Technologies
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 *
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 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version 2
 *  of the License, or (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 *
 *  FILE: megaraid_sas.h
 *
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 *  Authors: Avago Technologies
 *           Kashyap Desai <[email protected]>
 *           Sumit Saxena <[email protected]>
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 *
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 *  Send feedback to: [email protected]
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 *
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 *  Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
 *  San Jose, California 95131
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 */

#ifndef LSI_MEGARAID_SAS_H
#define LSI_MEGARAID_SAS_H

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/*
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 * MegaRAID SAS Driver meta data
 */
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#define MEGASAS_VERSION				"07.701.16.00-rc1"
#define MEGASAS_RELDATE				"February 2, 2017"
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/*
 * Device IDs
 */
#define	PCI_DEVICE_ID_LSI_SAS1078R		0x0060
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#define	PCI_DEVICE_ID_LSI_SAS1078DE		0x007C
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#define	PCI_DEVICE_ID_LSI_VERDE_ZCR		0x0413
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#define	PCI_DEVICE_ID_LSI_SAS1078GEN2		0x0078
#define	PCI_DEVICE_ID_LSI_SAS0079GEN2		0x0079
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#define	PCI_DEVICE_ID_LSI_SAS0073SKINNY		0x0073
#define	PCI_DEVICE_ID_LSI_SAS0071SKINNY		0x0071
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#define	PCI_DEVICE_ID_LSI_FUSION		0x005b
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#define PCI_DEVICE_ID_LSI_PLASMA		0x002f
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#define PCI_DEVICE_ID_LSI_INVADER		0x005d
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#define PCI_DEVICE_ID_LSI_FURY			0x005f
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#define PCI_DEVICE_ID_LSI_INTRUDER		0x00ce
#define PCI_DEVICE_ID_LSI_INTRUDER_24		0x00cf
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#define PCI_DEVICE_ID_LSI_CUTLASS_52		0x0052
#define PCI_DEVICE_ID_LSI_CUTLASS_53		0x0053
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#define PCI_DEVICE_ID_LSI_VENTURA		    0x0014
#define PCI_DEVICE_ID_LSI_HARPOON		    0x0016
#define PCI_DEVICE_ID_LSI_TOMCAT		    0x0017
#define PCI_DEVICE_ID_LSI_VENTURA_4PORT		0x001B
#define PCI_DEVICE_ID_LSI_CRUSADER_4PORT	0x001C
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/*
 * Intel HBA SSDIDs
 */
#define MEGARAID_INTEL_RS3DC080_SSDID		0x9360
#define MEGARAID_INTEL_RS3DC040_SSDID		0x9362
#define MEGARAID_INTEL_RS3SC008_SSDID		0x9380
#define MEGARAID_INTEL_RS3MC044_SSDID		0x9381
#define MEGARAID_INTEL_RS3WC080_SSDID		0x9341
#define MEGARAID_INTEL_RS3WC040_SSDID		0x9343
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#define MEGARAID_INTEL_RMS3BC160_SSDID		0x352B
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/*
 * Intruder HBA SSDIDs
 */
#define MEGARAID_INTRUDER_SSDID1		0x9371
#define MEGARAID_INTRUDER_SSDID2		0x9390
#define MEGARAID_INTRUDER_SSDID3		0x9370

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/*
 * Intel HBA branding
 */
#define MEGARAID_INTEL_RS3DC080_BRANDING	\
	"Intel(R) RAID Controller RS3DC080"
#define MEGARAID_INTEL_RS3DC040_BRANDING	\
	"Intel(R) RAID Controller RS3DC040"
#define MEGARAID_INTEL_RS3SC008_BRANDING	\
	"Intel(R) RAID Controller RS3SC008"
#define MEGARAID_INTEL_RS3MC044_BRANDING	\
	"Intel(R) RAID Controller RS3MC044"
#define MEGARAID_INTEL_RS3WC080_BRANDING	\
	"Intel(R) RAID Controller RS3WC080"
#define MEGARAID_INTEL_RS3WC040_BRANDING	\
	"Intel(R) RAID Controller RS3WC040"
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#define MEGARAID_INTEL_RMS3BC160_BRANDING	\
	"Intel(R) Integrated RAID Module RMS3BC160"
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/*
 * =====================================
 * MegaRAID SAS MFI firmware definitions
 * =====================================
 */

/*
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 * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
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 * protocol between the software and firmware. Commands are issued using
 * "message frames"
 */

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/*
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 * FW posts its state in upper 4 bits of outbound_msg_0 register
 */
#define MFI_STATE_MASK				0xF0000000
#define MFI_STATE_UNDEFINED			0x00000000
#define MFI_STATE_BB_INIT			0x10000000
#define MFI_STATE_FW_INIT			0x40000000
#define MFI_STATE_WAIT_HANDSHAKE		0x60000000
#define MFI_STATE_FW_INIT_2			0x70000000
#define MFI_STATE_DEVICE_SCAN			0x80000000
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#define MFI_STATE_BOOT_MESSAGE_PENDING		0x90000000
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#define MFI_STATE_FLUSH_CACHE			0xA0000000
#define MFI_STATE_READY				0xB0000000
#define MFI_STATE_OPERATIONAL			0xC0000000
#define MFI_STATE_FAULT				0xF0000000
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#define MFI_STATE_FORCE_OCR			0x00000080
#define MFI_STATE_DMADONE			0x00000008
#define MFI_STATE_CRASH_DUMP_DONE		0x00000004
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#define MFI_RESET_REQUIRED			0x00000001
#define MFI_RESET_ADAPTER			0x00000002
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#define MEGAMFI_FRAME_SIZE			64

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/*
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 * During FW init, clear pending cmds & reset state using inbound_msg_0
 *
 * ABORT	: Abort all pending cmds
 * READY	: Move from OPERATIONAL to READY state; discard queue info
 * MFIMODE	: Discard (possible) low MFA posted in 64-bit mode (??)
 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
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 * HOTPLUG	: Resume from Hotplug
 * MFI_STOP_ADP	: Send signal to FW to stop processing
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 */
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#define WRITE_SEQUENCE_OFFSET		(0x0000000FC) /* I20 */
#define HOST_DIAGNOSTIC_OFFSET		(0x000000F8)  /* I20 */
#define DIAG_WRITE_ENABLE			(0x00000080)
#define DIAG_RESET_ADAPTER			(0x00000004)

#define MFI_ADP_RESET				0x00000040
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#define MFI_INIT_ABORT				0x00000001
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#define MFI_INIT_READY				0x00000002
#define MFI_INIT_MFIMODE			0x00000004
#define MFI_INIT_CLEAR_HANDSHAKE		0x00000008
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#define MFI_INIT_HOTPLUG			0x00000010
#define MFI_STOP_ADP				0x00000020
#define MFI_RESET_FLAGS				MFI_INIT_READY| \
						MFI_INIT_MFIMODE| \
						MFI_INIT_ABORT
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#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
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/*
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 * MFI frame flags
 */
#define MFI_FRAME_POST_IN_REPLY_QUEUE		0x0000
#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE	0x0001
#define MFI_FRAME_SGL32				0x0000
#define MFI_FRAME_SGL64				0x0002
#define MFI_FRAME_SENSE32			0x0000
#define MFI_FRAME_SENSE64			0x0004
#define MFI_FRAME_DIR_NONE			0x0000
#define MFI_FRAME_DIR_WRITE			0x0008
#define MFI_FRAME_DIR_READ			0x0010
#define MFI_FRAME_DIR_BOTH			0x0018
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#define MFI_FRAME_IEEE                          0x0020
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/* Driver internal */
#define DRV_DCMD_POLLED_MODE		0x1
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#define DRV_DCMD_SKIP_REFIRE		0x2
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/*
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 * Definition for cmd_status
 */
#define MFI_CMD_STATUS_POLL_MODE		0xFF

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/*
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 * MFI command opcodes
 */
#define MFI_CMD_INIT				0x00
#define MFI_CMD_LD_READ				0x01
#define MFI_CMD_LD_WRITE			0x02
#define MFI_CMD_LD_SCSI_IO			0x03
#define MFI_CMD_PD_SCSI_IO			0x04
#define MFI_CMD_DCMD				0x05
#define MFI_CMD_ABORT				0x06
#define MFI_CMD_SMP				0x07
#define MFI_CMD_STP				0x08
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#define MFI_CMD_INVALID				0xff
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#define MR_DCMD_CTRL_GET_INFO			0x01010000
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#define MR_DCMD_LD_GET_LIST			0x03010000
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#define MR_DCMD_LD_LIST_QUERY			0x03010100
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#define MR_DCMD_CTRL_CACHE_FLUSH		0x01101000
#define MR_FLUSH_CTRL_CACHE			0x01
#define MR_FLUSH_DISK_CACHE			0x02

#define MR_DCMD_CTRL_SHUTDOWN			0x01050000
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#define MR_DCMD_HIBERNATE_SHUTDOWN		0x01060000
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#define MR_ENABLE_DRIVE_SPINDOWN		0x01

#define MR_DCMD_CTRL_EVENT_GET_INFO		0x01040100
#define MR_DCMD_CTRL_EVENT_GET			0x01040300
#define MR_DCMD_CTRL_EVENT_WAIT			0x01040500
#define MR_DCMD_LD_GET_PROPERTIES		0x03030000

#define MR_DCMD_CLUSTER				0x08000000
#define MR_DCMD_CLUSTER_RESET_ALL		0x08010100
#define MR_DCMD_CLUSTER_RESET_LD		0x08010200
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#define MR_DCMD_PD_LIST_QUERY                   0x02010100
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#define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS	0x01190100
#define MR_DRIVER_SET_APP_CRASHDUMP_MODE	(0xF0010000 | 0x0600)
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#define MR_DCMD_PD_GET_INFO			0x02020000
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/*
 * Global functions
 */
extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);


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/*
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 * MFI command completion codes
 */
enum MFI_STAT {
	MFI_STAT_OK = 0x00,
	MFI_STAT_INVALID_CMD = 0x01,
	MFI_STAT_INVALID_DCMD = 0x02,
	MFI_STAT_INVALID_PARAMETER = 0x03,
	MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
	MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
	MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
	MFI_STAT_APP_IN_USE = 0x07,
	MFI_STAT_APP_NOT_INITIALIZED = 0x08,
	MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
	MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
	MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
	MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
	MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
	MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
	MFI_STAT_FLASH_BUSY = 0x0f,
	MFI_STAT_FLASH_ERROR = 0x10,
	MFI_STAT_FLASH_IMAGE_BAD = 0x11,
	MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
	MFI_STAT_FLASH_NOT_OPEN = 0x13,
	MFI_STAT_FLASH_NOT_STARTED = 0x14,
	MFI_STAT_FLUSH_FAILED = 0x15,
	MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
	MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
	MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
	MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
	MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
	MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
	MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
	MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
	MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
	MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
	MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
	MFI_STAT_MFC_HW_ERROR = 0x21,
	MFI_STAT_NO_HW_PRESENT = 0x22,
	MFI_STAT_NOT_FOUND = 0x23,
	MFI_STAT_NOT_IN_ENCL = 0x24,
	MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
	MFI_STAT_PD_TYPE_WRONG = 0x26,
	MFI_STAT_PR_DISABLED = 0x27,
	MFI_STAT_ROW_INDEX_INVALID = 0x28,
	MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
	MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
	MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
	MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
	MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
	MFI_STAT_SCSI_IO_FAILED = 0x2e,
	MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
	MFI_STAT_SHUTDOWN_FAILED = 0x30,
	MFI_STAT_TIME_NOT_SET = 0x31,
	MFI_STAT_WRONG_STATE = 0x32,
	MFI_STAT_LD_OFFLINE = 0x33,
	MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
	MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
	MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
	MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
	MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
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	MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
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	MFI_STAT_INVALID_STATUS = 0xFF
};

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enum mfi_evt_class {
	MFI_EVT_CLASS_DEBUG =		-2,
	MFI_EVT_CLASS_PROGRESS =	-1,
	MFI_EVT_CLASS_INFO =		0,
	MFI_EVT_CLASS_WARNING =		1,
	MFI_EVT_CLASS_CRITICAL =	2,
	MFI_EVT_CLASS_FATAL =		3,
	MFI_EVT_CLASS_DEAD =		4
};

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/*
 * Crash dump related defines
 */
#define MAX_CRASH_DUMP_SIZE 512
#define CRASH_DMA_BUF_SIZE  (1024 * 1024)

enum MR_FW_CRASH_DUMP_STATE {
	UNAVAILABLE = 0,
	AVAILABLE = 1,
	COPYING = 2,
	COPIED = 3,
	COPY_ERROR = 4,
};

enum _MR_CRASH_BUF_STATUS {
	MR_CRASH_BUF_TURN_OFF = 0,
	MR_CRASH_BUF_TURN_ON = 1,
};

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/*
 * Number of mailbox bytes in DCMD message frame
 */
#define MFI_MBOX_SIZE				12

enum MR_EVT_CLASS {

	MR_EVT_CLASS_DEBUG = -2,
	MR_EVT_CLASS_PROGRESS = -1,
	MR_EVT_CLASS_INFO = 0,
	MR_EVT_CLASS_WARNING = 1,
	MR_EVT_CLASS_CRITICAL = 2,
	MR_EVT_CLASS_FATAL = 3,
	MR_EVT_CLASS_DEAD = 4,

};

enum MR_EVT_LOCALE {

	MR_EVT_LOCALE_LD = 0x0001,
	MR_EVT_LOCALE_PD = 0x0002,
	MR_EVT_LOCALE_ENCL = 0x0004,
	MR_EVT_LOCALE_BBU = 0x0008,
	MR_EVT_LOCALE_SAS = 0x0010,
	MR_EVT_LOCALE_CTRL = 0x0020,
	MR_EVT_LOCALE_CONFIG = 0x0040,
	MR_EVT_LOCALE_CLUSTER = 0x0080,
	MR_EVT_LOCALE_ALL = 0xffff,

};

enum MR_EVT_ARGS {

	MR_EVT_ARGS_NONE,
	MR_EVT_ARGS_CDB_SENSE,
	MR_EVT_ARGS_LD,
	MR_EVT_ARGS_LD_COUNT,
	MR_EVT_ARGS_LD_LBA,
	MR_EVT_ARGS_LD_OWNER,
	MR_EVT_ARGS_LD_LBA_PD_LBA,
	MR_EVT_ARGS_LD_PROG,
	MR_EVT_ARGS_LD_STATE,
	MR_EVT_ARGS_LD_STRIP,
	MR_EVT_ARGS_PD,
	MR_EVT_ARGS_PD_ERR,
	MR_EVT_ARGS_PD_LBA,
	MR_EVT_ARGS_PD_LBA_LD,
	MR_EVT_ARGS_PD_PROG,
	MR_EVT_ARGS_PD_STATE,
	MR_EVT_ARGS_PCI,
	MR_EVT_ARGS_RATE,
	MR_EVT_ARGS_STR,
	MR_EVT_ARGS_TIME,
	MR_EVT_ARGS_ECC,
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	MR_EVT_ARGS_LD_PROP,
	MR_EVT_ARGS_PD_SPARE,
	MR_EVT_ARGS_PD_INDEX,
	MR_EVT_ARGS_DIAG_PASS,
	MR_EVT_ARGS_DIAG_FAIL,
	MR_EVT_ARGS_PD_LBA_LBA,
	MR_EVT_ARGS_PORT_PHY,
	MR_EVT_ARGS_PD_MISSING,
	MR_EVT_ARGS_PD_ADDRESS,
	MR_EVT_ARGS_BITMAP,
	MR_EVT_ARGS_CONNECTOR,
	MR_EVT_ARGS_PD_PD,
	MR_EVT_ARGS_PD_FRU,
	MR_EVT_ARGS_PD_PATHINFO,
	MR_EVT_ARGS_PD_POWER_STATE,
	MR_EVT_ARGS_GENERIC,
};
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#define SGE_BUFFER_SIZE	4096
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#define MEGASAS_CLUSTER_ID_SIZE	16
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/*
 * define constants for device list query options
 */
enum MR_PD_QUERY_TYPE {
	MR_PD_QUERY_TYPE_ALL                = 0,
	MR_PD_QUERY_TYPE_STATE              = 1,
	MR_PD_QUERY_TYPE_POWER_STATE        = 2,
	MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
	MR_PD_QUERY_TYPE_SPEED              = 4,
	MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
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};

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enum MR_LD_QUERY_TYPE {
	MR_LD_QUERY_TYPE_ALL	         = 0,
	MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
	MR_LD_QUERY_TYPE_USED_TGT_IDS    = 2,
	MR_LD_QUERY_TYPE_CLUSTER_ACCESS  = 3,
	MR_LD_QUERY_TYPE_CLUSTER_LOCALE  = 4,
};


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#define MR_EVT_CFG_CLEARED                              0x0004
#define MR_EVT_LD_STATE_CHANGE                          0x0051
#define MR_EVT_PD_INSERTED                              0x005b
#define MR_EVT_PD_REMOVED                               0x0070
#define MR_EVT_LD_CREATED                               0x008a
#define MR_EVT_LD_DELETED                               0x008b
#define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
#define MR_EVT_LD_OFFLINE                               0x00fc
#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
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#define MR_EVT_CTRL_PROP_CHANGED			0x012f
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enum MR_PD_STATE {
	MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
	MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
	MR_PD_STATE_HOT_SPARE           = 0x02,
	MR_PD_STATE_OFFLINE             = 0x10,
	MR_PD_STATE_FAILED              = 0x11,
	MR_PD_STATE_REBUILD             = 0x14,
	MR_PD_STATE_ONLINE              = 0x18,
	MR_PD_STATE_COPYBACK            = 0x20,
	MR_PD_STATE_SYSTEM              = 0x40,
 };

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union MR_PD_REF {
	struct {
		u16	 deviceId;
		u16	 seqNum;
	} mrPdRef;
	u32	 ref;
};

/*
 * define the DDF Type bit structure
 */
union MR_PD_DDF_TYPE {
	 struct {
		union {
			struct {
#ifndef __BIG_ENDIAN_BITFIELD
				 u16	 forcedPDGUID:1;
				 u16	 inVD:1;
				 u16	 isGlobalSpare:1;
				 u16	 isSpare:1;
				 u16	 isForeign:1;
				 u16	 reserved:7;
				 u16	 intf:4;
#else
				 u16	 intf:4;
				 u16	 reserved:7;
				 u16	 isForeign:1;
				 u16	 isSpare:1;
				 u16	 isGlobalSpare:1;
				 u16	 inVD:1;
				 u16	 forcedPDGUID:1;
#endif
			 } pdType;
			 u16	 type;
		 };
		 u16	 reserved;
	 } ddf;
	 struct {
		 u32	reserved;
	 } nonDisk;
	 u32	 type;
} __packed;

/*
 * defines the progress structure
 */
union MR_PROGRESS {
	struct  {
		u16 progress;
		union {
			u16 elapsedSecs;
			u16 elapsedSecsForLastPercent;
		};
	} mrProgress;
	u32 w;
} __packed;

/*
 * defines the physical drive progress structure
 */
struct MR_PD_PROGRESS {
	struct {
#ifndef MFI_BIG_ENDIAN
		u32     rbld:1;
		u32     patrol:1;
		u32     clear:1;
		u32     copyBack:1;
		u32     erase:1;
		u32     locate:1;
		u32     reserved:26;
#else
		u32     reserved:26;
		u32     locate:1;
		u32     erase:1;
		u32     copyBack:1;
		u32     clear:1;
		u32     patrol:1;
		u32     rbld:1;
#endif
	} active;
	union MR_PROGRESS     rbld;
	union MR_PROGRESS     patrol;
	union {
		union MR_PROGRESS     clear;
		union MR_PROGRESS     erase;
	};

	struct {
#ifndef MFI_BIG_ENDIAN
		u32     rbld:1;
		u32     patrol:1;
		u32     clear:1;
		u32     copyBack:1;
		u32     erase:1;
		u32     reserved:27;
#else
		u32     reserved:27;
		u32     erase:1;
		u32     copyBack:1;
		u32     clear:1;
		u32     patrol:1;
		u32     rbld:1;
#endif
	} pause;

	union MR_PROGRESS     reserved[3];
} __packed;

struct  MR_PD_INFO {
	union MR_PD_REF	ref;
	u8 inquiryData[96];
	u8 vpdPage83[64];
	u8 notSupported;
	u8 scsiDevType;

	union {
		u8 connectedPortBitmap;
		u8 connectedPortNumbers;
	};

	u8 deviceSpeed;
	u32 mediaErrCount;
	u32 otherErrCount;
	u32 predFailCount;
	u32 lastPredFailEventSeqNum;

	u16 fwState;
	u8 disabledForRemoval;
	u8 linkSpeed;
	union MR_PD_DDF_TYPE state;

	struct {
		u8 count;
#ifndef __BIG_ENDIAN_BITFIELD
		u8 isPathBroken:4;
		u8 reserved3:3;
		u8 widePortCapable:1;
#else
		u8 widePortCapable:1;
		u8 reserved3:3;
		u8 isPathBroken:4;
#endif

		u8 connectorIndex[2];
		u8 reserved[4];
		u64 sasAddr[2];
		u8 reserved2[16];
	} pathInfo;

	u64 rawSize;
	u64 nonCoercedSize;
	u64 coercedSize;
	u16 enclDeviceId;
	u8 enclIndex;

	union {
		u8 slotNumber;
		u8 enclConnectorIndex;
	};

	struct MR_PD_PROGRESS progInfo;
	u8 badBlockTableFull;
	u8 unusableInCurrentConfig;
	u8 vpdPage83Ext[64];
	u8 powerState;
	u8 enclPosition;
	u32 allowedOps;
	u16 copyBackPartnerId;
	u16 enclPartnerDeviceId;
	struct {
#ifndef __BIG_ENDIAN_BITFIELD
		u16 fdeCapable:1;
		u16 fdeEnabled:1;
		u16 secured:1;
		u16 locked:1;
		u16 foreign:1;
		u16 needsEKM:1;
		u16 reserved:10;
#else
		u16 reserved:10;
		u16 needsEKM:1;
		u16 foreign:1;
		u16 locked:1;
		u16 secured:1;
		u16 fdeEnabled:1;
		u16 fdeCapable:1;
#endif
	} security;
	u8 mediaType;
	u8 notCertified;
	u8 bridgeVendor[8];
	u8 bridgeProductIdentification[16];
	u8 bridgeProductRevisionLevel[4];
	u8 satBridgeExists;

	u8 interfaceType;
	u8 temperature;
	u8 emulatedBlockSize;
	u16 userDataBlockSize;
	u16 reserved2;

	struct {
#ifndef __BIG_ENDIAN_BITFIELD
		u32 piType:3;
		u32 piFormatted:1;
		u32 piEligible:1;
		u32 NCQ:1;
		u32 WCE:1;
		u32 commissionedSpare:1;
		u32 emergencySpare:1;
		u32 ineligibleForSSCD:1;
		u32 ineligibleForLd:1;
		u32 useSSEraseType:1;
		u32 wceUnchanged:1;
		u32 supportScsiUnmap:1;
		u32 reserved:18;
#else
		u32 reserved:18;
		u32 supportScsiUnmap:1;
		u32 wceUnchanged:1;
		u32 useSSEraseType:1;
		u32 ineligibleForLd:1;
		u32 ineligibleForSSCD:1;
		u32 emergencySpare:1;
		u32 commissionedSpare:1;
		u32 WCE:1;
		u32 NCQ:1;
		u32 piEligible:1;
		u32 piFormatted:1;
		u32 piType:3;
#endif
	} properties;

	u64 shieldDiagCompletionTime;
	u8 shieldCounter;

	u8 linkSpeedOther;
	u8 reserved4[2];

	struct {
#ifndef __BIG_ENDIAN_BITFIELD
		u32 bbmErrCountSupported:1;
		u32 bbmErrCount:31;
#else
		u32 bbmErrCount:31;
		u32 bbmErrCountSupported:1;
#endif
	} bbmErr;

	u8 reserved1[512-428];
} __packed;
697

698 699 700 701 702 703 704 705 706 707 708 709
/*
 * Definition of structure used to expose attributes of VD or JBOD
 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
 * is fired by driver)
 */
struct MR_TARGET_PROPERTIES {
	u32    max_io_size_kb;
	u32    device_qdepth;
	u32    sector_size;
	u8     reserved[500];
} __packed;

710 711 712 713
 /*
 * defines the physical drive address structure
 */
struct MR_PD_ADDRESS {
714
	__le16	deviceId;
715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738
	u16     enclDeviceId;

	union {
		struct {
			u8  enclIndex;
			u8  slotNumber;
		} mrPdAddress;
		struct {
			u8  enclPosition;
			u8  enclConnectorIndex;
		} mrEnclAddress;
	};
	u8      scsiDevType;
	union {
		u8      connectedPortBitmap;
		u8      connectedPortNumbers;
	};
	u64     sasAddr[2];
} __packed;

/*
 * defines the physical drive list structure
 */
struct MR_PD_LIST {
739 740
	__le32		size;
	__le32		count;
741 742 743 744 745 746 747 748 749
	struct MR_PD_ADDRESS   addr[1];
} __packed;

struct megasas_pd_list {
	u16             tid;
	u8             driveType;
	u8             driveState;
} __packed;

750 751 752 753 754 755 756
 /*
 * defines the logical drive reference structure
 */
union  MR_LD_REF {
	struct {
		u8      targetId;
		u8      reserved;
757
		__le16     seqNum;
758
	};
759
	__le32     ref;
760 761 762 763 764 765
} __packed;

/*
 * defines the logical drive list structure
 */
struct MR_LD_LIST {
766 767
	__le32     ldCount;
	__le32     reserved;
768 769 770 771
	struct {
		union MR_LD_REF   ref;
		u8          state;
		u8          reserved[3];
772
		__le64		size;
773
	} ldList[MAX_LOGICAL_DRIVES_EXT];
774 775
} __packed;

776
struct MR_LD_TARGETID_LIST {
777 778
	__le32	size;
	__le32	count;
779
	u8	pad[3];
780
	u8	targetId[MAX_LOGICAL_DRIVES_EXT];
781 782 783
};


784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
/*
 * SAS controller properties
 */
struct megasas_ctrl_prop {

	u16 seq_num;
	u16 pred_fail_poll_interval;
	u16 intr_throttle_count;
	u16 intr_throttle_timeouts;
	u8 rebuild_rate;
	u8 patrol_read_rate;
	u8 bgi_rate;
	u8 cc_rate;
	u8 recon_rate;
	u8 cache_flush_interval;
	u8 spinup_drv_count;
	u8 spinup_delay;
	u8 cluster_enable;
	u8 coercion_mode;
	u8 alarm_enable;
	u8 disable_auto_rebuild;
	u8 disable_battery_warn;
	u8 ecc_bucket_size;
	u16 ecc_bucket_leak_rate;
	u8 restore_hotspare_on_insertion;
	u8 expose_encl_devices;
810 811 812 813 814 815 816 817 818 819 820 821 822
	u8 maintainPdFailHistory;
	u8 disallowHostRequestReordering;
	u8 abortCCOnError;
	u8 loadBalanceMode;
	u8 disableAutoDetectBackplane;

	u8 snapVDSpace;

	/*
	* Add properties that can be controlled by
	* a bit in the following structure.
	*/
	struct {
823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855
#if   defined(__BIG_ENDIAN_BITFIELD)
		u32     reserved:18;
		u32     enableJBOD:1;
		u32     disableSpinDownHS:1;
		u32     allowBootWithPinnedCache:1;
		u32     disableOnlineCtrlReset:1;
		u32     enableSecretKeyControl:1;
		u32     autoEnhancedImport:1;
		u32     enableSpinDownUnconfigured:1;
		u32     SSDPatrolReadEnabled:1;
		u32     SSDSMARTerEnabled:1;
		u32     disableNCQ:1;
		u32     useFdeOnly:1;
		u32     prCorrectUnconfiguredAreas:1;
		u32     SMARTerEnabled:1;
		u32     copyBackDisabled:1;
#else
		u32     copyBackDisabled:1;
		u32     SMARTerEnabled:1;
		u32     prCorrectUnconfiguredAreas:1;
		u32     useFdeOnly:1;
		u32     disableNCQ:1;
		u32     SSDSMARTerEnabled:1;
		u32     SSDPatrolReadEnabled:1;
		u32     enableSpinDownUnconfigured:1;
		u32     autoEnhancedImport:1;
		u32     enableSecretKeyControl:1;
		u32     disableOnlineCtrlReset:1;
		u32     allowBootWithPinnedCache:1;
		u32     disableSpinDownHS:1;
		u32     enableJBOD:1;
		u32     reserved:18;
#endif
856 857 858
	} OnOffProperties;
	u8 autoSnapVDSpace;
	u8 viewSpace;
859
	__le16 spinDownTime;
860
	u8  reserved[24];
861
} __packed;
862 863 864 865 866 867 868 869 870 871 872

/*
 * SAS controller information
 */
struct megasas_ctrl_info {

	/*
	 * PCI device information
	 */
	struct {

873 874 875 876
		__le16 vendor_id;
		__le16 device_id;
		__le16 sub_vendor_id;
		__le16 sub_device_id;
877 878 879 880 881 882 883 884 885 886 887 888 889
		u8 reserved[24];

	} __attribute__ ((packed)) pci;

	/*
	 * Host interface information
	 */
	struct {

		u8 PCIX:1;
		u8 PCIE:1;
		u8 iSCSI:1;
		u8 SAS_3G:1;
890 891
		u8 SRIOV:1;
		u8 reserved_0:3;
892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916
		u8 reserved_1[6];
		u8 port_count;
		u64 port_addr[8];

	} __attribute__ ((packed)) host_interface;

	/*
	 * Device (backend) interface information
	 */
	struct {

		u8 SPI:1;
		u8 SAS_3G:1;
		u8 SATA_1_5G:1;
		u8 SATA_3G:1;
		u8 reserved_0:4;
		u8 reserved_1[6];
		u8 port_count;
		u64 port_addr[8];

	} __attribute__ ((packed)) device_interface;

	/*
	 * List of components residing in flash. All str are null terminated
	 */
917 918
	__le32 image_check_word;
	__le32 image_component_count;
919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934

	struct {

		char name[8];
		char version[32];
		char build_date[16];
		char built_time[16];

	} __attribute__ ((packed)) image_component[8];

	/*
	 * List of flash components that have been flashed on the card, but
	 * are not in use, pending reset of the adapter. This list will be
	 * empty if a flash operation has not occurred. All stings are null
	 * terminated
	 */
935
	__le32 pending_image_component_count;
936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967

	struct {

		char name[8];
		char version[32];
		char build_date[16];
		char build_time[16];

	} __attribute__ ((packed)) pending_image_component[8];

	u8 max_arms;
	u8 max_spans;
	u8 max_arrays;
	u8 max_lds;

	char product_name[80];
	char serial_no[32];

	/*
	 * Other physical/controller/operation information. Indicates the
	 * presence of the hardware
	 */
	struct {

		u32 bbu:1;
		u32 alarm:1;
		u32 nvram:1;
		u32 uart:1;
		u32 reserved:28;

	} __attribute__ ((packed)) hw_present;

968
	__le32 current_fw_time;
969 970 971 972

	/*
	 * Maximum data transfer sizes
	 */
973 974 975
	__le16 max_concurrent_cmds;
	__le16 max_sge_count;
	__le32 max_request_size;
976 977 978 979

	/*
	 * Logical and physical device counts
	 */
980 981 982
	__le16 ld_present_count;
	__le16 ld_degraded_count;
	__le16 ld_offline_count;
983

984 985 986 987
	__le16 pd_present_count;
	__le16 pd_disk_present_count;
	__le16 pd_disk_pred_failure_count;
	__le16 pd_disk_failed_count;
988 989 990 991

	/*
	 * Memory size information
	 */
992 993 994
	__le16 nvram_size;
	__le16 memory_size;
	__le16 flash_size;
995 996 997 998

	/*
	 * Error counters
	 */
999 1000
	__le16 mem_correctable_error_count;
	__le16 mem_uncorrectable_error_count;
1001 1002 1003 1004 1005 1006 1007 1008 1009 1010

	/*
	 * Cluster information
	 */
	u8 cluster_permitted;
	u8 cluster_active;

	/*
	 * Additional max data transfer sizes
	 */
1011
	__le16 max_strips_per_io;
1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103

	/*
	 * Controller capabilities structures
	 */
	struct {

		u32 raid_level_0:1;
		u32 raid_level_1:1;
		u32 raid_level_5:1;
		u32 raid_level_1E:1;
		u32 raid_level_6:1;
		u32 reserved:27;

	} __attribute__ ((packed)) raid_levels;

	struct {

		u32 rbld_rate:1;
		u32 cc_rate:1;
		u32 bgi_rate:1;
		u32 recon_rate:1;
		u32 patrol_rate:1;
		u32 alarm_control:1;
		u32 cluster_supported:1;
		u32 bbu:1;
		u32 spanning_allowed:1;
		u32 dedicated_hotspares:1;
		u32 revertible_hotspares:1;
		u32 foreign_config_import:1;
		u32 self_diagnostic:1;
		u32 mixed_redundancy_arr:1;
		u32 global_hot_spares:1;
		u32 reserved:17;

	} __attribute__ ((packed)) adapter_operations;

	struct {

		u32 read_policy:1;
		u32 write_policy:1;
		u32 io_policy:1;
		u32 access_policy:1;
		u32 disk_cache_policy:1;
		u32 reserved:27;

	} __attribute__ ((packed)) ld_operations;

	struct {

		u8 min;
		u8 max;
		u8 reserved[2];

	} __attribute__ ((packed)) stripe_sz_ops;

	struct {

		u32 force_online:1;
		u32 force_offline:1;
		u32 force_rebuild:1;
		u32 reserved:29;

	} __attribute__ ((packed)) pd_operations;

	struct {

		u32 ctrl_supports_sas:1;
		u32 ctrl_supports_sata:1;
		u32 allow_mix_in_encl:1;
		u32 allow_mix_in_ld:1;
		u32 allow_sata_in_cluster:1;
		u32 reserved:27;

	} __attribute__ ((packed)) pd_mix_support;

	/*
	 * Define ECC single-bit-error bucket information
	 */
	u8 ecc_bucket_count;
	u8 reserved_2[11];

	/*
	 * Include the controller properties (changeable items)
	 */
	struct megasas_ctrl_prop properties;

	/*
	 * Define FW pkg version (set in envt v'bles on OEM basis)
	 */
	char package_version[0x60];


1104 1105 1106 1107 1108 1109 1110
	/*
	* If adapterOperations.supportMoreThan8Phys is set,
	* and deviceInterface.portCount is greater than 8,
	* SAS Addrs for first 8 ports shall be populated in
	* deviceInterface.portAddr, and the rest shall be
	* populated in deviceInterfacePortAddr2.
	*/
1111
	__le64	    deviceInterfacePortAddr2[8]; /*6a0h */
1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
	u8          reserved3[128];              /*6e0h */

	struct {                                /*760h */
		u16 minPdRaidLevel_0:4;
		u16 maxPdRaidLevel_0:12;

		u16 minPdRaidLevel_1:4;
		u16 maxPdRaidLevel_1:12;

		u16 minPdRaidLevel_5:4;
		u16 maxPdRaidLevel_5:12;

		u16 minPdRaidLevel_1E:4;
		u16 maxPdRaidLevel_1E:12;

		u16 minPdRaidLevel_6:4;
		u16 maxPdRaidLevel_6:12;

		u16 minPdRaidLevel_10:4;
		u16 maxPdRaidLevel_10:12;

		u16 minPdRaidLevel_50:4;
		u16 maxPdRaidLevel_50:12;

		u16 minPdRaidLevel_60:4;
		u16 maxPdRaidLevel_60:12;

		u16 minPdRaidLevel_1E_RLQ0:4;
		u16 maxPdRaidLevel_1E_RLQ0:12;

		u16 minPdRaidLevel_1E0_RLQ0:4;
		u16 maxPdRaidLevel_1E0_RLQ0:12;

		u16 reserved[6];
	} pdsForRaidLevels;

1148 1149 1150 1151
	__le16 maxPds;                          /*780h */
	__le16 maxDedHSPs;                      /*782h */
	__le16 maxGlobalHSP;                    /*784h */
	__le16 ddfSize;                         /*786h */
1152 1153 1154 1155 1156 1157
	u8  maxLdsPerArray;                     /*788h */
	u8  partitionsInDDF;                    /*789h */
	u8  lockKeyBinding;                     /*78ah */
	u8  maxPITsPerLd;                       /*78bh */
	u8  maxViewsPerLd;                      /*78ch */
	u8  maxTargetId;                        /*78dh */
1158
	__le16 maxBvlVdSize;                    /*78eh */
1159

1160 1161
	__le16 maxConfigurableSSCSize;          /*790h */
	__le16 currentSSCsize;                  /*792h */
1162 1163 1164

	char    expanderFwVersion[12];          /*794h */

1165
	__le16 PFKTrialTimeRemaining;           /*7A0h */
1166

1167
	__le16 cacheMemorySize;                 /*7A2h */
1168 1169

	struct {                                /*7A4h */
1170
#if   defined(__BIG_ENDIAN_BITFIELD)
1171 1172 1173 1174 1175 1176
		u32     reserved:5;
		u32	activePassive:2;
		u32	supportConfigAutoBalance:1;
		u32	mpio:1;
		u32	supportDataLDonSSCArray:1;
		u32	supportPointInTimeProgress:1;
1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198
		u32     supportUnevenSpans:1;
		u32     dedicatedHotSparesLimited:1;
		u32     headlessMode:1;
		u32     supportEmulatedDrives:1;
		u32     supportResetNow:1;
		u32     realTimeScheduler:1;
		u32     supportSSDPatrolRead:1;
		u32     supportPerfTuning:1;
		u32     disableOnlinePFKChange:1;
		u32     supportJBOD:1;
		u32     supportBootTimePFKChange:1;
		u32     supportSetLinkSpeed:1;
		u32     supportEmergencySpares:1;
		u32     supportSuspendResumeBGops:1;
		u32     blockSSDWriteCacheChange:1;
		u32     supportShieldState:1;
		u32     supportLdBBMInfo:1;
		u32     supportLdPIType3:1;
		u32     supportLdPIType2:1;
		u32     supportLdPIType1:1;
		u32     supportPIcontroller:1;
#else
1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
		u32     supportPIcontroller:1;
		u32     supportLdPIType1:1;
		u32     supportLdPIType2:1;
		u32     supportLdPIType3:1;
		u32     supportLdBBMInfo:1;
		u32     supportShieldState:1;
		u32     blockSSDWriteCacheChange:1;
		u32     supportSuspendResumeBGops:1;
		u32     supportEmergencySpares:1;
		u32     supportSetLinkSpeed:1;
		u32     supportBootTimePFKChange:1;
		u32     supportJBOD:1;
		u32     disableOnlinePFKChange:1;
		u32     supportPerfTuning:1;
		u32     supportSSDPatrolRead:1;
		u32     realTimeScheduler:1;

		u32     supportResetNow:1;
		u32     supportEmulatedDrives:1;
		u32     headlessMode:1;
		u32     dedicatedHotSparesLimited:1;


		u32     supportUnevenSpans:1;
1223 1224 1225 1226 1227 1228
		u32	supportPointInTimeProgress:1;
		u32	supportDataLDonSSCArray:1;
		u32	mpio:1;
		u32	supportConfigAutoBalance:1;
		u32	activePassive:2;
		u32     reserved:5;
1229
#endif
1230 1231 1232 1233 1234 1235 1236
	} adapterOperations2;

	u8  driverVersion[32];                  /*7A8h */
	u8  maxDAPdCountSpinup60;               /*7C8h */
	u8  temperatureROC;                     /*7C9h */
	u8  temperatureCtrl;                    /*7CAh */
	u8  reserved4;                          /*7CBh */
1237
	__le16 maxConfigurablePds;              /*7CCh */
1238 1239 1240 1241 1242 1243 1244 1245


	u8  reserved5[2];                       /*0x7CDh */

	/*
	* HA cluster information
	*/
	struct {
1246
#if defined(__BIG_ENDIAN_BITFIELD)
1247 1248
		u32     reserved:25;
		u32     passive:1;
1249 1250 1251 1252 1253 1254 1255
		u32     premiumFeatureMismatch:1;
		u32     ctrlPropIncompatible:1;
		u32     fwVersionMismatch:1;
		u32     hwIncompatible:1;
		u32     peerIsIncompatible:1;
		u32     peerIsPresent:1;
#else
1256 1257 1258 1259 1260 1261
		u32     peerIsPresent:1;
		u32     peerIsIncompatible:1;
		u32     hwIncompatible:1;
		u32     fwVersionMismatch:1;
		u32     ctrlPropIncompatible:1;
		u32     premiumFeatureMismatch:1;
1262 1263
		u32     passive:1;
		u32     reserved:25;
1264
#endif
1265 1266
	} cluster;

1267
	char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1268 1269 1270 1271 1272 1273
	struct {
		u8  maxVFsSupported;            /*0x7E4*/
		u8  numVFsEnabled;              /*0x7E5*/
		u8  requestorId;                /*0x7E6 0:PF, 1:VF1, 2:VF2*/
		u8  reserved;                   /*0x7E7*/
	} iov;
1274

1275 1276
	struct {
#if defined(__BIG_ENDIAN_BITFIELD)
1277 1278
		u32     reserved:7;
		u32     useSeqNumJbodFP:1;
1279 1280 1281 1282
		u32     supportExtendedSSCSize:1;
		u32     supportDiskCacheSettingForSysPDs:1;
		u32     supportCPLDUpdate:1;
		u32     supportTTYLogCompression:1;
1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295
		u32     discardCacheDuringLDDelete:1;
		u32     supportSecurityonJBOD:1;
		u32     supportCacheBypassModes:1;
		u32     supportDisableSESMonitoring:1;
		u32     supportForceFlash:1;
		u32     supportNVDRAM:1;
		u32     supportDrvActivityLEDSetting:1;
		u32     supportAllowedOpsforDrvRemoval:1;
		u32     supportHOQRebuild:1;
		u32     supportForceTo512e:1;
		u32     supportNVCacheErase:1;
		u32     supportDebugQueue:1;
		u32     supportSwZone:1;
1296
		u32     supportCrashDump:1;
1297 1298 1299 1300 1301
		u32     supportMaxExtLDs:1;
		u32     supportT10RebuildAssist:1;
		u32     supportDisableImmediateIO:1;
		u32     supportThermalPollInterval:1;
		u32     supportPersonalityChange:2;
1302
#else
1303 1304 1305 1306
		u32     supportPersonalityChange:2;
		u32     supportThermalPollInterval:1;
		u32     supportDisableImmediateIO:1;
		u32     supportT10RebuildAssist:1;
1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321
		u32	supportMaxExtLDs:1;
		u32	supportCrashDump:1;
		u32     supportSwZone:1;
		u32     supportDebugQueue:1;
		u32     supportNVCacheErase:1;
		u32     supportForceTo512e:1;
		u32     supportHOQRebuild:1;
		u32     supportAllowedOpsforDrvRemoval:1;
		u32     supportDrvActivityLEDSetting:1;
		u32     supportNVDRAM:1;
		u32     supportForceFlash:1;
		u32     supportDisableSESMonitoring:1;
		u32     supportCacheBypassModes:1;
		u32     supportSecurityonJBOD:1;
		u32     discardCacheDuringLDDelete:1;
1322 1323 1324 1325
		u32     supportTTYLogCompression:1;
		u32     supportCPLDUpdate:1;
		u32     supportDiskCacheSettingForSysPDs:1;
		u32     supportExtendedSSCSize:1;
1326 1327
		u32     useSeqNumJbodFP:1;
		u32     reserved:7;
1328 1329 1330
#endif
	} adapterOperations3;

1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378
	struct {
#if defined(__BIG_ENDIAN_BITFIELD)
	u8 reserved:7;
	/* Indicates whether the CPLD image is part of
	 *  the package and stored in flash
	 */
	u8 cpld_in_flash:1;
#else
	u8 cpld_in_flash:1;
	u8 reserved:7;
#endif
	u8 reserved1[3];
	/* Null terminated string. Has the version
	 *  information if cpld_in_flash = FALSE
	 */
	u8 userCodeDefinition[12];
	} cpld;  /* Valid only if upgradableCPLD is TRUE */

	struct {
	#if defined(__BIG_ENDIAN_BITFIELD)
		u16 reserved:8;
		u16 fw_swaps_bbu_vpd_info:1;
		u16 support_pd_map_target_id:1;
		u16 support_ses_ctrl_in_multipathcfg:1;
		u16 image_upload_supported:1;
		u16 support_encrypted_mfc:1;
		u16 supported_enc_algo:1;
		u16 support_ibutton_less:1;
		u16 ctrl_info_ext_supported:1;
	#else

		u16 ctrl_info_ext_supported:1;
		u16 support_ibutton_less:1;
		u16 supported_enc_algo:1;
		u16 support_encrypted_mfc:1;
		u16 image_upload_supported:1;
		/* FW supports LUN based association and target port based */
		u16 support_ses_ctrl_in_multipathcfg:1;
		/* association for the SES device connected in multipath mode */
		/* FW defines Jbod target Id within MR_PD_CFG_SEQ */
		u16 support_pd_map_target_id:1;
		/* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
		 *  provide the data in little endian order
		 */
		u16 fw_swaps_bbu_vpd_info:1;
		u16 reserved:8;
	#endif
		} adapter_operations4;
1379
	u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1380
} __packed;
1381 1382 1383 1384 1385 1386 1387

/*
 * ===============================
 * MegaRAID SAS driver definitions
 * ===============================
 */
#define MEGASAS_MAX_PD_CHANNELS			2
1388
#define MEGASAS_MAX_LD_CHANNELS			2
1389 1390 1391 1392 1393
#define MEGASAS_MAX_CHANNELS			(MEGASAS_MAX_PD_CHANNELS + \
						MEGASAS_MAX_LD_CHANNELS)
#define MEGASAS_MAX_DEV_PER_CHANNEL		128
#define MEGASAS_DEFAULT_INIT_ID			-1
#define MEGASAS_MAX_LUN				8
1394
#define MEGASAS_DEFAULT_CMD_PER_LUN		256
1395 1396
#define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
						MEGASAS_MAX_DEV_PER_CHANNEL)
1397 1398
#define MEGASAS_MAX_LD_IDS			(MEGASAS_MAX_LD_CHANNELS * \
						MEGASAS_MAX_DEV_PER_CHANNEL)
1399

1400
#define MEGASAS_MAX_SECTORS                    (2*1024)
1401
#define MEGASAS_MAX_SECTORS_IEEE		(2*128)
1402 1403
#define MEGASAS_DBG_LVL				1

1404 1405
#define MEGASAS_FW_BUSY				1

1406 1407 1408
/* Driver's internal Logging levels*/
#define OCR_LOGS    (1 << 0)

1409 1410
#define SCAN_PD_CHANNEL	0x1
#define SCAN_VD_CHANNEL	0x2
1411

1412
#define MEGASAS_KDUMP_QUEUE_DEPTH               100
1413 1414
#define MR_LARGE_IO_MIN_SIZE			(32 * 1024)
#define MR_R1_LDIO_PIGGYBACK_DEFAULT		4
1415

1416 1417 1418 1419 1420 1421 1422
enum MR_SCSI_CMD_TYPE {
	READ_WRITE_LDIO = 0,
	NON_READ_WRITE_LDIO = 1,
	READ_WRITE_SYSPDIO = 2,
	NON_READ_WRITE_SYSPDIO = 3,
};

1423 1424 1425 1426 1427
enum DCMD_TIMEOUT_ACTION {
	INITIATE_OCR = 0,
	KILL_ADAPTER = 1,
	IGNORE_TIMEOUT = 2,
};
1428 1429 1430 1431 1432 1433

enum FW_BOOT_CONTEXT {
	PROBE_CONTEXT = 0,
	OCR_CONTEXT = 1,
};

1434 1435 1436 1437
/* Frame Type */
#define IO_FRAME				0
#define PTHRU_FRAME				1

1438 1439 1440 1441 1442 1443 1444 1445
/*
 * When SCSI mid-layer calls driver's reset routine, driver waits for
 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
 * that the driver cannot _actually_ abort or reset pending commands. While
 * it is waiting for the commands to complete, it prints a diagnostic message
 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
 */
#define MEGASAS_RESET_WAIT_TIME			180
1446
#define MEGASAS_INTERNAL_CMD_WAIT_TIME		180
1447 1448
#define	MEGASAS_RESET_NOTICE_INTERVAL		5
#define MEGASAS_IOCTL_CMD			0
1449
#define MEGASAS_DEFAULT_CMD_TIMEOUT		90
1450
#define MEGASAS_THROTTLE_QUEUE_DEPTH		16
1451
#define MEGASAS_BLOCKED_CMD_TIMEOUT		60
1452 1453 1454 1455 1456 1457 1458 1459
/*
 * FW reports the maximum of number of commands that it can accept (maximum
 * commands that can be outstanding) at any time. The driver must report a
 * lower number to the mid layer because it can issue a few internal commands
 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
 * is shown below
 */
#define MEGASAS_INT_CMDS			32
1460
#define MEGASAS_SKINNY_INT_CMDS			5
1461
#define MEGASAS_FUSION_INTERNAL_CMDS		8
1462
#define MEGASAS_FUSION_IOCTL_CMDS		3
1463
#define MEGASAS_MFI_IOCTL_CMDS			27
1464

1465
#define MEGASAS_MAX_MSIX_QUEUES			128
1466 1467 1468 1469 1470 1471
/*
 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
 * SGLs based on the size of dma_addr_t
 */
#define IS_DMA64				(sizeof(dma_addr_t) == 8)

1472 1473 1474 1475 1476 1477
#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT		0x00000001

#define MFI_INTR_FLAG_REPLY_MESSAGE			0x00000001
#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE		0x00000002
#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT	0x00000004

1478
#define MFI_OB_INTR_STATUS_MASK			0x00000002
1479
#define MFI_POLL_TIMEOUT_SECS			60
1480
#define MFI_IO_TIMEOUT_SECS			180
1481 1482 1483
#define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF	(5 * HZ)
#define MEGASAS_OCR_SETTLE_TIME_VF		(1000 * 30)
#define MEGASAS_ROUTINE_WAIT_TIME_VF		300
1484
#define MFI_REPLY_1078_MESSAGE_INTERRUPT	0x80000000
1485 1486
#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT	0x00000001
#define MFI_GEN2_ENABLE_INTERRUPT_MASK		(0x00000001 | 0x00000004)
1487 1488
#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT	0x40000000
#define MFI_SKINNY_ENABLE_INTERRUPT_MASK	(0x00000001)
1489

1490 1491 1492
#define MFI_1068_PCSR_OFFSET			0x84
#define MFI_1068_FW_HANDSHAKE_OFFSET		0x64
#define MFI_1068_FW_READY			0xDDDD0000
1493 1494 1495 1496 1497

#define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
#define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
#define MR_MAX_MSIX_REG_ARRAY                   16
1498
#define MR_RDPQ_MODE_OFFSET			0X00800000
1499 1500 1501 1502 1503 1504

#define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT	16
#define MR_MAX_RAID_MAP_SIZE_MASK		0x1FF
#define MR_MIN_MAP_SIZE				0x10000
/* 64k */

1505 1506
#define MR_CAN_HANDLE_SYNC_CACHE_OFFSET		0X01000000

1507 1508 1509 1510
/*
* register set for both 1068 and 1078 controllers
* structure extended for 1078 registers
*/
1511

1512
struct megasas_register_set {
1513 1514 1515 1516
	u32	doorbell;                       /*0000h*/
	u32	fusion_seq_offset;		/*0004h*/
	u32	fusion_host_diag;		/*0008h*/
	u32	reserved_01;			/*000Ch*/
1517

1518 1519 1520 1521
	u32 	inbound_msg_0;			/*0010h*/
	u32 	inbound_msg_1;			/*0014h*/
	u32 	outbound_msg_0;			/*0018h*/
	u32 	outbound_msg_1;			/*001Ch*/
1522

1523 1524 1525
	u32 	inbound_doorbell;		/*0020h*/
	u32 	inbound_intr_status;		/*0024h*/
	u32 	inbound_intr_mask;		/*0028h*/
1526

1527 1528 1529
	u32 	outbound_doorbell;		/*002Ch*/
	u32 	outbound_intr_status;		/*0030h*/
	u32 	outbound_intr_mask;		/*0034h*/
1530

1531
	u32 	reserved_1[2];			/*0038h*/
1532

1533 1534
	u32 	inbound_queue_port;		/*0040h*/
	u32 	outbound_queue_port;		/*0044h*/
1535

1536 1537 1538
	u32	reserved_2[9];			/*0048h*/
	u32	reply_post_host_index;		/*006Ch*/
	u32	reserved_2_2[12];		/*0070h*/
1539

1540
	u32 	outbound_doorbell_clear;	/*00A0h*/
1541

1542 1543 1544
	u32 	reserved_3[3];			/*00A4h*/

	u32 	outbound_scratch_pad ;		/*00B0h*/
1545
	u32	outbound_scratch_pad_2;         /*00B4h*/
1546
	u32	outbound_scratch_pad_3;         /*00B8h*/
1547
	u32	outbound_scratch_pad_4;         /*00BCh*/
1548 1549 1550 1551 1552 1553


	u32 	inbound_low_queue_port ;	/*00C0h*/

	u32 	inbound_high_queue_port ;	/*00C4h*/

1554
	u32 inbound_single_queue_port;	/*00C8h*/
1555 1556 1557 1558
	u32	res_6[11];			/*CCh*/
	u32	host_diag;
	u32	seq_offset;
	u32 	index_registers[807];		/*00CCh*/
1559 1560 1561 1562
} __attribute__ ((packed));

struct megasas_sge32 {

1563 1564
	__le32 phys_addr;
	__le32 length;
1565 1566 1567 1568 1569

} __attribute__ ((packed));

struct megasas_sge64 {

1570 1571
	__le64 phys_addr;
	__le32 length;
1572 1573 1574

} __attribute__ ((packed));

1575
struct megasas_sge_skinny {
1576 1577 1578
	__le64 phys_addr;
	__le32 length;
	__le32 flag;
1579 1580
} __packed;

1581 1582 1583 1584
union megasas_sgl {

	struct megasas_sge32 sge32[1];
	struct megasas_sge64 sge64[1];
1585
	struct megasas_sge_skinny sge_skinny[1];
1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600

} __attribute__ ((packed));

struct megasas_header {

	u8 cmd;			/*00h */
	u8 sense_len;		/*01h */
	u8 cmd_status;		/*02h */
	u8 scsi_status;		/*03h */

	u8 target_id;		/*04h */
	u8 lun;			/*05h */
	u8 cdb_len;		/*06h */
	u8 sge_count;		/*07h */

1601 1602
	__le32 context;		/*08h */
	__le32 pad_0;		/*0Ch */
1603

1604 1605 1606
	__le16 flags;		/*10h */
	__le16 timeout;		/*12h */
	__le32 data_xferlen;	/*14h */
1607 1608 1609 1610 1611 1612 1613 1614 1615 1616

} __attribute__ ((packed));

union megasas_sgl_frame {

	struct megasas_sge32 sge32[8];
	struct megasas_sge64 sge64[5];

} __attribute__ ((packed));

1617 1618
typedef union _MFI_CAPABILITIES {
	struct {
1619
#if   defined(__BIG_ENDIAN_BITFIELD)
1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
	u32     reserved:19;
	u32 support_pd_map_target_id:1;
	u32     support_qd_throttling:1;
	u32     support_fp_rlbypass:1;
	u32     support_vfid_in_ioframe:1;
	u32     support_ext_io_size:1;
	u32		support_ext_queue_depth:1;
	u32     security_protocol_cmds_fw:1;
	u32     support_core_affinity:1;
	u32     support_ndrive_r1_lb:1;
	u32		support_max_255lds:1;
	u32		support_fastpath_wb:1;
	u32     support_additional_msix:1;
	u32     support_fp_remote_lun:1;
1634
#else
1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648
	u32     support_fp_remote_lun:1;
	u32     support_additional_msix:1;
	u32		support_fastpath_wb:1;
	u32		support_max_255lds:1;
	u32     support_ndrive_r1_lb:1;
	u32     support_core_affinity:1;
	u32     security_protocol_cmds_fw:1;
	u32		support_ext_queue_depth:1;
	u32     support_ext_io_size:1;
	u32     support_vfid_in_ioframe:1;
	u32     support_fp_rlbypass:1;
	u32     support_qd_throttling:1;
	u32	support_pd_map_target_id:1;
	u32     reserved:19;
1649
#endif
1650
	} mfi_capabilities;
1651
	__le32		reg;
1652 1653
} MFI_CAPABILITIES;

1654 1655 1656 1657 1658 1659 1660
struct megasas_init_frame {

	u8 cmd;			/*00h */
	u8 reserved_0;		/*01h */
	u8 cmd_status;		/*02h */

	u8 reserved_1;		/*03h */
1661
	MFI_CAPABILITIES driver_operations; /*04h*/
1662

1663 1664
	__le32 context;		/*08h */
	__le32 pad_0;		/*0Ch */
1665

1666 1667 1668
	__le16 flags;		/*10h */
	__le16 reserved_3;		/*12h */
	__le32 data_xfer_len;	/*14h */
1669

1670 1671 1672 1673 1674 1675 1676 1677
	__le32 queue_info_new_phys_addr_lo;	/*18h */
	__le32 queue_info_new_phys_addr_hi;	/*1Ch */
	__le32 queue_info_old_phys_addr_lo;	/*20h */
	__le32 queue_info_old_phys_addr_hi;	/*24h */
	__le32 reserved_4[2];	/*28h */
	__le32 system_info_lo;      /*30h */
	__le32 system_info_hi;      /*34h */
	__le32 reserved_5[2];	/*38h */
1678 1679 1680 1681 1682

} __attribute__ ((packed));

struct megasas_init_queue_info {

1683 1684
	__le32 init_flags;		/*00h */
	__le32 reply_queue_entries;	/*04h */
1685

1686 1687 1688 1689 1690 1691
	__le32 reply_queue_start_phys_addr_lo;	/*08h */
	__le32 reply_queue_start_phys_addr_hi;	/*0Ch */
	__le32 producer_index_phys_addr_lo;	/*10h */
	__le32 producer_index_phys_addr_hi;	/*14h */
	__le32 consumer_index_phys_addr_lo;	/*18h */
	__le32 consumer_index_phys_addr_hi;	/*1Ch */
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706

} __attribute__ ((packed));

struct megasas_io_frame {

	u8 cmd;			/*00h */
	u8 sense_len;		/*01h */
	u8 cmd_status;		/*02h */
	u8 scsi_status;		/*03h */

	u8 target_id;		/*04h */
	u8 access_byte;		/*05h */
	u8 reserved_0;		/*06h */
	u8 sge_count;		/*07h */

1707 1708
	__le32 context;		/*08h */
	__le32 pad_0;		/*0Ch */
1709

1710 1711 1712
	__le16 flags;		/*10h */
	__le16 timeout;		/*12h */
	__le32 lba_count;	/*14h */
1713

1714 1715
	__le32 sense_buf_phys_addr_lo;	/*18h */
	__le32 sense_buf_phys_addr_hi;	/*1Ch */
1716

1717 1718