atmel-mci.c 74.3 KB
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/*
 * Atmel MultiMedia Card Interface driver
 *
 * Copyright (C) 2004-2008 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/blkdev.h>
#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
#include <linux/module.h>
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#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
#include <linux/scatterlist.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/stat.h>
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#include <linux/types.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sdio.h>
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#include <linux/atmel-mci.h>
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#include <linux/atmel_pdc.h>
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#include <linux/pm.h>
#include <linux/pm_runtime.h>
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#include <linux/pinctrl/consumer.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
#include <asm/unaligned.h>

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/*
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 * Superset of MCI IP registers integrated in Atmel AT91 Processor
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 * Registers and bitfields marked with [2] are only available in MCI2
 */

/* MCI Register Definitions */
#define	ATMCI_CR			0x0000	/* Control */
#define		ATMCI_CR_MCIEN			BIT(0)		/* MCI Enable */
#define		ATMCI_CR_MCIDIS			BIT(1)		/* MCI Disable */
#define		ATMCI_CR_PWSEN			BIT(2)		/* Power Save Enable */
#define		ATMCI_CR_PWSDIS			BIT(3)		/* Power Save Disable */
#define		ATMCI_CR_SWRST			BIT(7)		/* Software Reset */
#define	ATMCI_MR			0x0004	/* Mode */
#define		ATMCI_MR_CLKDIV(x)		((x) <<  0)	/* Clock Divider */
#define		ATMCI_MR_PWSDIV(x)		((x) <<  8)	/* Power Saving Divider */
#define		ATMCI_MR_RDPROOF		BIT(11)		/* Read Proof */
#define		ATMCI_MR_WRPROOF		BIT(12)		/* Write Proof */
#define		ATMCI_MR_PDCFBYTE		BIT(13)		/* Force Byte Transfer */
#define		ATMCI_MR_PDCPADV		BIT(14)		/* Padding Value */
#define		ATMCI_MR_PDCMODE		BIT(15)		/* PDC-oriented Mode */
#define		ATMCI_MR_CLKODD(x)		((x) << 16)	/* LSB of Clock Divider */
#define	ATMCI_DTOR			0x0008	/* Data Timeout */
#define		ATMCI_DTOCYC(x)			((x) <<  0)	/* Data Timeout Cycles */
#define		ATMCI_DTOMUL(x)			((x) <<  4)	/* Data Timeout Multiplier */
#define	ATMCI_SDCR			0x000c	/* SD Card / SDIO */
#define		ATMCI_SDCSEL_SLOT_A		(0 <<  0)	/* Select SD slot A */
#define		ATMCI_SDCSEL_SLOT_B		(1 <<  0)	/* Select SD slot A */
#define		ATMCI_SDCSEL_MASK		(3 <<  0)
#define		ATMCI_SDCBUS_1BIT		(0 <<  6)	/* 1-bit data bus */
#define		ATMCI_SDCBUS_4BIT		(2 <<  6)	/* 4-bit data bus */
#define		ATMCI_SDCBUS_8BIT		(3 <<  6)	/* 8-bit data bus[2] */
#define		ATMCI_SDCBUS_MASK		(3 <<  6)
#define	ATMCI_ARGR			0x0010	/* Command Argument */
#define	ATMCI_CMDR			0x0014	/* Command */
#define		ATMCI_CMDR_CMDNB(x)		((x) <<  0)	/* Command Opcode */
#define		ATMCI_CMDR_RSPTYP_NONE		(0 <<  6)	/* No response */
#define		ATMCI_CMDR_RSPTYP_48BIT		(1 <<  6)	/* 48-bit response */
#define		ATMCI_CMDR_RSPTYP_136BIT	(2 <<  6)	/* 136-bit response */
#define		ATMCI_CMDR_SPCMD_INIT		(1 <<  8)	/* Initialization command */
#define		ATMCI_CMDR_SPCMD_SYNC		(2 <<  8)	/* Synchronized command */
#define		ATMCI_CMDR_SPCMD_INT		(4 <<  8)	/* Interrupt command */
#define		ATMCI_CMDR_SPCMD_INTRESP	(5 <<  8)	/* Interrupt response */
#define		ATMCI_CMDR_OPDCMD		(1 << 11)	/* Open Drain */
#define		ATMCI_CMDR_MAXLAT_5CYC		(0 << 12)	/* Max latency 5 cycles */
#define		ATMCI_CMDR_MAXLAT_64CYC		(1 << 12)	/* Max latency 64 cycles */
#define		ATMCI_CMDR_START_XFER		(1 << 16)	/* Start data transfer */
#define		ATMCI_CMDR_STOP_XFER		(2 << 16)	/* Stop data transfer */
#define		ATMCI_CMDR_TRDIR_WRITE		(0 << 18)	/* Write data */
#define		ATMCI_CMDR_TRDIR_READ		(1 << 18)	/* Read data */
#define		ATMCI_CMDR_BLOCK		(0 << 19)	/* Single-block transfer */
#define		ATMCI_CMDR_MULTI_BLOCK		(1 << 19)	/* Multi-block transfer */
#define		ATMCI_CMDR_STREAM		(2 << 19)	/* MMC Stream transfer */
#define		ATMCI_CMDR_SDIO_BYTE		(4 << 19)	/* SDIO Byte transfer */
#define		ATMCI_CMDR_SDIO_BLOCK		(5 << 19)	/* SDIO Block transfer */
#define		ATMCI_CMDR_SDIO_SUSPEND		(1 << 24)	/* SDIO Suspend Command */
#define		ATMCI_CMDR_SDIO_RESUME		(2 << 24)	/* SDIO Resume Command */
#define	ATMCI_BLKR			0x0018	/* Block */
#define		ATMCI_BCNT(x)			((x) <<  0)	/* Data Block Count */
#define		ATMCI_BLKLEN(x)			((x) << 16)	/* Data Block Length */
#define	ATMCI_CSTOR			0x001c	/* Completion Signal Timeout[2] */
#define		ATMCI_CSTOCYC(x)		((x) <<  0)	/* CST cycles */
#define		ATMCI_CSTOMUL(x)		((x) <<  4)	/* CST multiplier */
#define	ATMCI_RSPR			0x0020	/* Response 0 */
#define	ATMCI_RSPR1			0x0024	/* Response 1 */
#define	ATMCI_RSPR2			0x0028	/* Response 2 */
#define	ATMCI_RSPR3			0x002c	/* Response 3 */
#define	ATMCI_RDR			0x0030	/* Receive Data */
#define	ATMCI_TDR			0x0034	/* Transmit Data */
#define	ATMCI_SR			0x0040	/* Status */
#define	ATMCI_IER			0x0044	/* Interrupt Enable */
#define	ATMCI_IDR			0x0048	/* Interrupt Disable */
#define	ATMCI_IMR			0x004c	/* Interrupt Mask */
#define		ATMCI_CMDRDY			BIT(0)		/* Command Ready */
#define		ATMCI_RXRDY			BIT(1)		/* Receiver Ready */
#define		ATMCI_TXRDY			BIT(2)		/* Transmitter Ready */
#define		ATMCI_BLKE			BIT(3)		/* Data Block Ended */
#define		ATMCI_DTIP			BIT(4)		/* Data Transfer In Progress */
#define		ATMCI_NOTBUSY			BIT(5)		/* Data Not Busy */
#define		ATMCI_ENDRX			BIT(6)		/* End of RX Buffer */
#define		ATMCI_ENDTX			BIT(7)		/* End of TX Buffer */
#define		ATMCI_SDIOIRQA			BIT(8)		/* SDIO IRQ in slot A */
#define		ATMCI_SDIOIRQB			BIT(9)		/* SDIO IRQ in slot B */
#define		ATMCI_SDIOWAIT			BIT(12)		/* SDIO Read Wait Operation Status */
#define		ATMCI_CSRCV			BIT(13)		/* CE-ATA Completion Signal Received */
#define		ATMCI_RXBUFF			BIT(14)		/* RX Buffer Full */
#define		ATMCI_TXBUFE			BIT(15)		/* TX Buffer Empty */
#define		ATMCI_RINDE			BIT(16)		/* Response Index Error */
#define		ATMCI_RDIRE			BIT(17)		/* Response Direction Error */
#define		ATMCI_RCRCE			BIT(18)		/* Response CRC Error */
#define		ATMCI_RENDE			BIT(19)		/* Response End Bit Error */
#define		ATMCI_RTOE			BIT(20)		/* Response Time-Out Error */
#define		ATMCI_DCRCE			BIT(21)		/* Data CRC Error */
#define		ATMCI_DTOE			BIT(22)		/* Data Time-Out Error */
#define		ATMCI_CSTOE			BIT(23)		/* Completion Signal Time-out Error */
#define		ATMCI_BLKOVRE			BIT(24)		/* DMA Block Overrun Error */
#define		ATMCI_DMADONE			BIT(25)		/* DMA Transfer Done */
#define		ATMCI_FIFOEMPTY			BIT(26)		/* FIFO Empty Flag */
#define		ATMCI_XFRDONE			BIT(27)		/* Transfer Done Flag */
#define		ATMCI_ACKRCV			BIT(28)		/* Boot Operation Acknowledge Received */
#define		ATMCI_ACKRCVE			BIT(29)		/* Boot Operation Acknowledge Error */
#define		ATMCI_OVRE			BIT(30)		/* RX Overrun Error */
#define		ATMCI_UNRE			BIT(31)		/* TX Underrun Error */
#define	ATMCI_DMA			0x0050	/* DMA Configuration[2] */
#define		ATMCI_DMA_OFFSET(x)		((x) <<  0)	/* DMA Write Buffer Offset */
#define		ATMCI_DMA_CHKSIZE(x)		((x) <<  4)	/* DMA Channel Read and Write Chunk Size */
#define		ATMCI_DMAEN			BIT(8)	/* DMA Hardware Handshaking Enable */
#define	ATMCI_CFG			0x0054	/* Configuration[2] */
#define		ATMCI_CFG_FIFOMODE_1DATA	BIT(0)		/* MCI Internal FIFO control mode */
#define		ATMCI_CFG_FERRCTRL_COR		BIT(4)		/* Flow Error flag reset control mode */
#define		ATMCI_CFG_HSMODE		BIT(8)		/* High Speed Mode */
#define		ATMCI_CFG_LSYNC			BIT(12)		/* Synchronize on the last block */
#define	ATMCI_WPMR			0x00e4	/* Write Protection Mode[2] */
#define		ATMCI_WP_EN			BIT(0)		/* WP Enable */
#define		ATMCI_WP_KEY			(0x4d4349 << 8)	/* WP Key */
#define	ATMCI_WPSR			0x00e8	/* Write Protection Status[2] */
#define		ATMCI_GET_WP_VS(x)		((x) & 0x0f)
#define		ATMCI_GET_WP_VSRC(x)		(((x) >> 8) & 0xffff)
#define	ATMCI_VERSION			0x00FC  /* Version */
#define	ATMCI_FIFO_APERTURE		0x0200	/* FIFO Aperture[2] */

/* This is not including the FIFO Aperture on MCI2 */
#define	ATMCI_REGS_SIZE		0x100

/* Register access macros */
#define	atmci_readl(port, reg)				\
	__raw_readl((port)->regs + reg)
#define	atmci_writel(port, reg, value)			\
	__raw_writel((value), (port)->regs + reg)

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#define AUTOSUSPEND_DELAY	50

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#define ATMCI_DATA_ERROR_FLAGS	(ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
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#define ATMCI_DMA_THRESHOLD	16
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enum {
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	EVENT_CMD_RDY = 0,
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	EVENT_XFER_COMPLETE,
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	EVENT_NOTBUSY,
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	EVENT_DATA_ERROR,
};

enum atmel_mci_state {
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	STATE_IDLE = 0,
	STATE_SENDING_CMD,
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	STATE_DATA_XFER,
	STATE_WAITING_NOTBUSY,
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	STATE_SENDING_STOP,
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	STATE_END_REQUEST,
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};

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enum atmci_xfer_dir {
	XFER_RECEIVE = 0,
	XFER_TRANSMIT,
};

enum atmci_pdc_buf {
	PDC_FIRST_BUF = 0,
	PDC_SECOND_BUF,
};

struct atmel_mci_caps {
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	bool    has_dma_conf_reg;
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	bool    has_pdc;
	bool    has_cfg_reg;
	bool    has_cstor_reg;
	bool    has_highspeed;
	bool    has_rwproof;
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	bool	has_odd_clk_div;
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	bool	has_bad_data_ordering;
	bool	need_reset_after_xfer;
	bool	need_blksz_mul_4;
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	bool	need_notbusy_for_read_ops;
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};

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struct atmel_mci_dma {
	struct dma_chan			*chan;
	struct dma_async_tx_descriptor	*data_desc;
};

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/**
 * struct atmel_mci - MMC controller state shared between all slots
 * @lock: Spinlock protecting the queue and associated data.
 * @regs: Pointer to MMIO registers.
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 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
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 * @pio_offset: Offset into the current scatterlist entry.
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 * @buffer: Buffer used if we don't have the r/w proof capability. We
 *      don't have the time to switch pdc buffers so we have to use only
 *      one buffer for the full transaction.
 * @buf_size: size of the buffer.
 * @phys_buf_addr: buffer address needed for pdc.
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 * @cur_slot: The slot which is currently using the controller.
 * @mrq: The request currently being processed on @cur_slot,
 *	or NULL if the controller is idle.
 * @cmd: The command currently being sent to the card, or NULL.
 * @data: The data currently being transferred, or NULL if no data
 *	transfer is in progress.
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 * @data_size: just data->blocks * data->blksz.
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 * @dma: DMA client state.
 * @data_chan: DMA channel being used for the current data transfer.
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 * @cmd_status: Snapshot of SR taken upon completion of the current
 *	command. Only valid when EVENT_CMD_COMPLETE is pending.
 * @data_status: Snapshot of SR taken upon completion of the current
 *	data transfer. Only valid when EVENT_DATA_COMPLETE or
 *	EVENT_DATA_ERROR is pending.
 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 *	to be sent.
 * @tasklet: Tasklet running the request state machine.
 * @pending_events: Bitmask of events flagged by the interrupt handler
 *	to be processed by the tasklet.
 * @completed_events: Bitmask of events which the state machine has
 *	processed.
 * @state: Tasklet state.
 * @queue: List of slots waiting for access to the controller.
 * @need_clock_update: Update the clock rate before the next request.
 * @need_reset: Reset controller before next request.
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 * @timer: Timer to balance the data timeout error flag which cannot rise.
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 * @mode_reg: Value of the MR register.
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 * @cfg_reg: Value of the CFG register.
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 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 *	rate and timeout calculations.
 * @mapbase: Physical address of the MMIO registers.
 * @mck: The peripheral bus clock hooked up to the MMC controller.
 * @pdev: Platform device associated with the MMC controller.
 * @slot: Slots sharing this MMC controller.
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 * @caps: MCI capabilities depending on MCI version.
 * @prepare_data: function to setup MCI before data transfer which
 * depends on MCI capabilities.
 * @submit_data: function to start data transfer which depends on MCI
 * capabilities.
 * @stop_transfer: function to stop data transfer which depends on MCI
 * capabilities.
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 *
 * Locking
 * =======
 *
 * @lock is a softirq-safe spinlock protecting @queue as well as
 * @cur_slot, @mrq and @state. These must always be updated
 * at the same time while holding @lock.
 *
 * @lock also protects mode_reg and need_clock_update since these are
 * used to synchronize mode register updates with the queue
 * processing.
 *
 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
 * and must always be written at the same time as the slot is added to
 * @queue.
 *
 * @pending_events and @completed_events are accessed using atomic bit
 * operations, so they don't need any locking.
 *
 * None of the fields touched by the interrupt handler need any
 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 * interrupts must be disabled and @data_status updated with a
 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
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 * CMDRDY interrupt must be disabled and @cmd_status updated with a
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 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 * bytes_xfered field of @data must be written. This is ensured by
 * using barriers.
 */
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struct atmel_mci {
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	spinlock_t		lock;
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	void __iomem		*regs;

	struct scatterlist	*sg;
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	unsigned int		sg_len;
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	unsigned int		pio_offset;
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	unsigned int		*buffer;
	unsigned int		buf_size;
	dma_addr_t		buf_phys_addr;
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	struct atmel_mci_slot	*cur_slot;
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	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;
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	unsigned int		data_size;
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	struct atmel_mci_dma	dma;
	struct dma_chan		*data_chan;
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	struct dma_slave_config	dma_conf;
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	u32			cmd_status;
	u32			data_status;
	u32			stop_cmdr;

	struct tasklet_struct	tasklet;
	unsigned long		pending_events;
	unsigned long		completed_events;
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	enum atmel_mci_state	state;
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	struct list_head	queue;
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	bool			need_clock_update;
	bool			need_reset;
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	struct timer_list	timer;
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	u32			mode_reg;
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	u32			cfg_reg;
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	unsigned long		bus_hz;
	unsigned long		mapbase;
	struct clk		*mck;
	struct platform_device	*pdev;
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	struct atmel_mci_slot	*slot[ATMCI_MAX_NR_SLOTS];
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	struct atmel_mci_caps   caps;

	u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
	void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
	void (*stop_transfer)(struct atmel_mci *host);
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};

/**
 * struct atmel_mci_slot - MMC slot state
 * @mmc: The mmc_host representing this slot.
 * @host: The MMC controller this slot is using.
 * @sdc_reg: Value of SDCR to be written before using this slot.
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 * @sdio_irq: SDIO irq mask for this slot.
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 * @mrq: mmc_request currently being processed or waiting to be
 *	processed, or NULL when the slot is idle.
 * @queue_node: List node for placing this node in the @queue list of
 *	&struct atmel_mci.
 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
 * @flags: Random state bits associated with the slot.
 * @detect_pin: GPIO pin used for card detection, or negative if not
 *	available.
 * @wp_pin: GPIO pin used for card write protect sending, or negative
 *	if not available.
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 * @detect_is_active_high: The state of the detect pin when it is active.
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 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
 */
struct atmel_mci_slot {
	struct mmc_host		*mmc;
	struct atmel_mci	*host;

	u32			sdc_reg;
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	u32			sdio_irq;
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	struct mmc_request	*mrq;
	struct list_head	queue_node;

	unsigned int		clock;
	unsigned long		flags;
#define ATMCI_CARD_PRESENT	0
#define ATMCI_CARD_NEED_INIT	1
#define ATMCI_SHUTDOWN		2

	int			detect_pin;
	int			wp_pin;
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	bool			detect_is_active_high;
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	struct timer_list	detect_timer;
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};

#define atmci_test_and_clear_pending(host, event)		\
	test_and_clear_bit(event, &host->pending_events)
#define atmci_set_completed(host, event)			\
	set_bit(event, &host->completed_events)
#define atmci_set_pending(host, event)				\
	set_bit(event, &host->pending_events)

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/*
 * The debugfs stuff below is mostly optimized away when
 * CONFIG_DEBUG_FS is not set.
 */
static int atmci_req_show(struct seq_file *s, void *v)
{
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	struct atmel_mci_slot	*slot = s->private;
	struct mmc_request	*mrq;
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	struct mmc_command	*cmd;
	struct mmc_command	*stop;
	struct mmc_data		*data;

	/* Make sure we get a consistent snapshot */
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	spin_lock_bh(&slot->host->lock);
	mrq = slot->mrq;
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	if (mrq) {
		cmd = mrq->cmd;
		data = mrq->data;
		stop = mrq->stop;

		if (cmd)
			seq_printf(s,
				"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
				cmd->opcode, cmd->arg, cmd->flags,
				cmd->resp[0], cmd->resp[1], cmd->resp[2],
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				cmd->resp[3], cmd->error);
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		if (data)
			seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
				data->bytes_xfered, data->blocks,
				data->blksz, data->flags, data->error);
		if (stop)
			seq_printf(s,
				"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
				stop->opcode, stop->arg, stop->flags,
				stop->resp[0], stop->resp[1], stop->resp[2],
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				stop->resp[3], stop->error);
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	}

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	spin_unlock_bh(&slot->host->lock);
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	return 0;
}

static int atmci_req_open(struct inode *inode, struct file *file)
{
	return single_open(file, atmci_req_show, inode->i_private);
}

static const struct file_operations atmci_req_fops = {
	.owner		= THIS_MODULE,
	.open		= atmci_req_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static void atmci_show_status_reg(struct seq_file *s,
		const char *regname, u32 value)
{
	static const char	*sr_bit[] = {
		[0]	= "CMDRDY",
		[1]	= "RXRDY",
		[2]	= "TXRDY",
		[3]	= "BLKE",
		[4]	= "DTIP",
		[5]	= "NOTBUSY",
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		[6]	= "ENDRX",
		[7]	= "ENDTX",
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		[8]	= "SDIOIRQA",
		[9]	= "SDIOIRQB",
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		[12]	= "SDIOWAIT",
		[14]	= "RXBUFF",
		[15]	= "TXBUFE",
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		[16]	= "RINDE",
		[17]	= "RDIRE",
		[18]	= "RCRCE",
		[19]	= "RENDE",
		[20]	= "RTOE",
		[21]	= "DCRCE",
		[22]	= "DTOE",
486 487 488 489 490
		[23]	= "CSTOE",
		[24]	= "BLKOVRE",
		[25]	= "DMADONE",
		[26]	= "FIFOEMPTY",
		[27]	= "XFRDONE",
491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511
		[30]	= "OVRE",
		[31]	= "UNRE",
	};
	unsigned int		i;

	seq_printf(s, "%s:\t0x%08x", regname, value);
	for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
		if (value & (1 << i)) {
			if (sr_bit[i])
				seq_printf(s, " %s", sr_bit[i]);
			else
				seq_puts(s, " UNKNOWN");
		}
	}
	seq_putc(s, '\n');
}

static int atmci_regs_show(struct seq_file *s, void *v)
{
	struct atmel_mci	*host = s->private;
	u32			*buf;
512 513
	int			ret = 0;

514

515
	buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
516 517 518
	if (!buf)
		return -ENOMEM;

519 520
	pm_runtime_get_sync(&host->pdev->dev);

521 522 523 524 525 526
	/*
	 * Grab a more or less consistent snapshot. Note that we're
	 * not disabling interrupts, so IMR and SR may not be
	 * consistent.
	 */
	spin_lock_bh(&host->lock);
527
	memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
528
	spin_unlock_bh(&host->lock);
529

530 531
	pm_runtime_mark_last_busy(&host->pdev->dev);
	pm_runtime_put_autosuspend(&host->pdev->dev);
532

533
	seq_printf(s, "MR:\t0x%08x%s%s ",
534 535
			buf[ATMCI_MR / 4],
			buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
536 537 538 539 540 541 542 543
			buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
	if (host->caps.has_odd_clk_div)
		seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
				((buf[ATMCI_MR / 4] & 0xff) << 1)
				| ((buf[ATMCI_MR / 4] >> 16) & 1));
	else
		seq_printf(s, "CLKDIV=%u\n",
				(buf[ATMCI_MR / 4] & 0xff));
544 545 546
	seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
	seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
	seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
547
	seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
548 549 550
			buf[ATMCI_BLKR / 4],
			buf[ATMCI_BLKR / 4] & 0xffff,
			(buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
551
	if (host->caps.has_cstor_reg)
552
		seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
553 554 555

	/* Don't read RSPR and RDR; it will consume the data there */

556 557
	atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
	atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
558

559
	if (host->caps.has_dma_conf_reg) {
560 561
		u32 val;

562
		val = buf[ATMCI_DMA / 4];
563 564 565 566
		seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
				val, val & 3,
				((val >> 4) & 3) ?
					1 << (((val >> 4) & 3) + 1) : 1,
567
				val & ATMCI_DMAEN ? " DMAEN" : "");
568 569 570
	}
	if (host->caps.has_cfg_reg) {
		u32 val;
571

572
		val = buf[ATMCI_CFG / 4];
573 574
		seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
				val,
575 576 577 578
				val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
				val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
				val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
				val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
579 580
	}

581 582
	kfree(buf);

583
	return ret;
584 585 586 587 588 589 590 591 592 593 594 595 596 597 598
}

static int atmci_regs_open(struct inode *inode, struct file *file)
{
	return single_open(file, atmci_regs_show, inode->i_private);
}

static const struct file_operations atmci_regs_fops = {
	.owner		= THIS_MODULE,
	.open		= atmci_regs_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

599
static void atmci_init_debugfs(struct atmel_mci_slot *slot)
600
{
601 602 603 604
	struct mmc_host		*mmc = slot->mmc;
	struct atmel_mci	*host = slot->host;
	struct dentry		*root;
	struct dentry		*node;
605 606 607 608 609 610 611 612 613 614 615 616

	root = mmc->debugfs_root;
	if (!root)
		return;

	node = debugfs_create_file("regs", S_IRUSR, root, host,
			&atmci_regs_fops);
	if (IS_ERR(node))
		return;
	if (!node)
		goto err;

617
	node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
618 619 620
	if (!node)
		goto err;

621 622 623 624
	node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
	if (!node)
		goto err;

625 626 627 628 629 630 631 632 633 634 635 636 637
	node = debugfs_create_x32("pending_events", S_IRUSR, root,
				     (u32 *)&host->pending_events);
	if (!node)
		goto err;

	node = debugfs_create_x32("completed_events", S_IRUSR, root,
				     (u32 *)&host->completed_events);
	if (!node)
		goto err;

	return;

err:
638
	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
639
}
640

641 642 643 644 645 646 647 648
#if defined(CONFIG_OF)
static const struct of_device_id atmci_dt_ids[] = {
	{ .compatible = "atmel,hsmci" },
	{ /* sentinel */ }
};

MODULE_DEVICE_TABLE(of, atmci_dt_ids);

649
static struct mci_platform_data*
650 651 652 653 654 655 656 657 658 659 660 661 662
atmci_of_init(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device_node *cnp;
	struct mci_platform_data *pdata;
	u32 slot_id;

	if (!np) {
		dev_err(&pdev->dev, "device node not found\n");
		return ERR_PTR(-EINVAL);
	}

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
663
	if (!pdata)
664 665 666 667
		return ERR_PTR(-ENOMEM);

	for_each_child_of_node(np, cnp) {
		if (of_property_read_u32(cnp, "reg", &slot_id)) {
668 669
			dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
				 cnp);
670 671 672 673 674 675
			continue;
		}

		if (slot_id >= ATMCI_MAX_NR_SLOTS) {
			dev_warn(&pdev->dev, "can't have more than %d slots\n",
			         ATMCI_MAX_NR_SLOTS);
676
			of_node_put(cnp);
677 678 679 680 681 682 683 684 685 686 687 688 689
			break;
		}

		if (of_property_read_u32(cnp, "bus-width",
		                         &pdata->slot[slot_id].bus_width))
			pdata->slot[slot_id].bus_width = 1;

		pdata->slot[slot_id].detect_pin =
			of_get_named_gpio(cnp, "cd-gpios", 0);

		pdata->slot[slot_id].detect_is_active_high =
			of_property_read_bool(cnp, "cd-inverted");

690 691 692
		pdata->slot[slot_id].non_removable =
			of_property_read_bool(cnp, "non-removable");

693 694 695 696 697 698 699 700 701 702 703 704 705 706
		pdata->slot[slot_id].wp_pin =
			of_get_named_gpio(cnp, "wp-gpios", 0);
	}

	return pdata;
}
#else /* CONFIG_OF */
static inline struct mci_platform_data*
atmci_of_init(struct platform_device *dev)
{
	return ERR_PTR(-EINVAL);
}
#endif

707 708 709 710 711
static inline unsigned int atmci_get_version(struct atmel_mci *host)
{
	return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
}

712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734
/*
 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
 * 8 -> 3, 16 -> 4.
 *
 * This can be done by finding most significant bit set.
 */
static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
						 unsigned int maxburst)
{
	unsigned int version = atmci_get_version(host);
	unsigned int offset = 2;

	if (version >= 0x600)
		offset = 1;

	if (maxburst > 1)
		return fls(maxburst) - offset;
	else
		return 0;
}

735
static void atmci_timeout_timer(struct timer_list *t)
736 737 738
{
	struct atmel_mci *host;

739
	host = from_timer(host, t, timer);
740 741 742 743 744 745

	dev_dbg(&host->pdev->dev, "software timeout\n");

	if (host->mrq->cmd->data) {
		host->mrq->cmd->data->error = -ETIMEDOUT;
		host->data = NULL;
746 747 748 749 750 751 752
		/*
		 * With some SDIO modules, sometimes DMA transfer hangs. If
		 * stop_transfer() is not called then the DMA request is not
		 * removed, following ones are queued and never computed.
		 */
		if (host->state == STATE_DATA_XFER)
			host->stop_transfer(host);
753 754 755 756 757 758 759 760 761 762
	} else {
		host->mrq->cmd->error = -ETIMEDOUT;
		host->cmd = NULL;
	}
	host->need_reset = 1;
	host->state = STATE_END_REQUEST;
	smp_wmb();
	tasklet_schedule(&host->tasklet);
}

763
static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
764 765
					unsigned int ns)
{
766 767 768 769 770 771 772 773
	/*
	 * It is easier here to use us instead of ns for the timeout,
	 * it prevents from overflows during calculation.
	 */
	unsigned int us = DIV_ROUND_UP(ns, 1000);

	/* Maximum clock frequency is host->bus_hz/2 */
	return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
774 775 776
}

static void atmci_set_timeout(struct atmel_mci *host,
777
		struct atmel_mci_slot *slot, struct mmc_data *data)
778 779 780 781 782 783 784 785
{
	static unsigned	dtomul_to_shift[] = {
		0, 4, 7, 8, 10, 12, 16, 20
	};
	unsigned	timeout;
	unsigned	dtocyc;
	unsigned	dtomul;

786 787
	timeout = atmci_ns_to_clocks(host, data->timeout_ns)
		+ data->timeout_clks;
788 789 790 791 792 793 794 795 796 797 798 799 800

	for (dtomul = 0; dtomul < 8; dtomul++) {
		unsigned shift = dtomul_to_shift[dtomul];
		dtocyc = (timeout + (1 << shift) - 1) >> shift;
		if (dtocyc < 15)
			break;
	}

	if (dtomul >= 8) {
		dtomul = 7;
		dtocyc = 15;
	}

801
	dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
802
			dtocyc << dtomul_to_shift[dtomul]);
803
	atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
804 805 806 807 808 809 810 811 812 813 814 815 816
}

/*
 * Return mask with command flags to be enabled for this command.
 */
static u32 atmci_prepare_command(struct mmc_host *mmc,
				 struct mmc_command *cmd)
{
	struct mmc_data	*data;
	u32		cmdr;

	cmd->error = -EINPROGRESS;

817
	cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
818 819 820

	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136)
821
			cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
822
		else
823
			cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
824 825 826 827 828 829 830
	}

	/*
	 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
	 * it's too difficult to determine whether this is an ACMD or
	 * not. Better make it 64.
	 */
831
	cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
832 833

	if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
834
		cmdr |= ATMCI_CMDR_OPDCMD;
835 836 837

	data = cmd->data;
	if (data) {
838
		cmdr |= ATMCI_CMDR_START_XFER;
839 840

		if (cmd->opcode == SD_IO_RW_EXTENDED) {
841
			cmdr |= ATMCI_CMDR_SDIO_BLOCK;
842
		} else {
843
			if (data->blocks > 1)
844
				cmdr |= ATMCI_CMDR_MULTI_BLOCK;
845
			else
846
				cmdr |= ATMCI_CMDR_BLOCK;
847
		}
848 849

		if (data->flags & MMC_DATA_READ)
850
			cmdr |= ATMCI_CMDR_TRDIR_READ;
851 852 853 854 855
	}

	return cmdr;
}

856
static void atmci_send_command(struct atmel_mci *host,
857
		struct mmc_command *cmd, u32 cmd_flags)
858 859 860 861
{
	WARN_ON(host->cmd);
	host->cmd = cmd;

862
	dev_vdbg(&host->pdev->dev,
863 864 865
			"start command: ARGR=0x%08x CMDR=0x%08x\n",
			cmd->arg, cmd_flags);

866 867
	atmci_writel(host, ATMCI_ARGR, cmd->arg);
	atmci_writel(host, ATMCI_CMDR, cmd_flags);
868 869
}

870
static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
871
{
872
	dev_dbg(&host->pdev->dev, "send stop command\n");
873
	atmci_send_command(host, data->stop, host->stop_cmdr);
874
	atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
875 876
}

877 878 879 880 881 882 883 884
/*
 * Configure given PDC buffer taking care of alignement issues.
 * Update host->data_size and host->sg.
 */
static void atmci_pdc_set_single_buf(struct atmel_mci *host,
	enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
{
	u32 pointer_reg, counter_reg;
885
	unsigned int buf_size;
886 887 888 889 890 891 892 893 894 895

	if (dir == XFER_RECEIVE) {
		pointer_reg = ATMEL_PDC_RPR;
		counter_reg = ATMEL_PDC_RCR;
	} else {
		pointer_reg = ATMEL_PDC_TPR;
		counter_reg = ATMEL_PDC_TCR;
	}

	if (buf_nb == PDC_SECOND_BUF) {
896 897
		pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
		counter_reg += ATMEL_PDC_SCND_BUF_OFF;
898 899
	}

900 901 902 903 904 905 906 907 908
	if (!host->caps.has_rwproof) {
		buf_size = host->buf_size;
		atmci_writel(host, pointer_reg, host->buf_phys_addr);
	} else {
		buf_size = sg_dma_len(host->sg);
		atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
	}

	if (host->data_size <= buf_size) {
909 910 911 912 913 914 915 916 917 918 919
		if (host->data_size & 0x3) {
			/* If size is different from modulo 4, transfer bytes */
			atmci_writel(host, counter_reg, host->data_size);
			atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
		} else {
			/* Else transfer 32-bits words */
			atmci_writel(host, counter_reg, host->data_size / 4);
		}
		host->data_size = 0;
	} else {
		/* We assume the size of a page is 32-bits aligned */
920 921
		atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
		host->data_size -= sg_dma_len(host->sg);
922 923 924 925 926 927 928 929 930 931 932
		if (host->data_size)
			host->sg = sg_next(host->sg);
	}
}

/*
 * Configure PDC buffer according to the data size ie configuring one or two
 * buffers. Don't use this function if you want to configure only the second
 * buffer. In this case, use atmci_pdc_set_single_buf.
 */
static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
933
{
934 935 936 937 938 939 940 941 942 943 944
	atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
	if (host->data_size)
		atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
}

/*
 * Unmap sg lists, called when transfer is finished.
 */
static void atmci_pdc_cleanup(struct atmel_mci *host)
{
	struct mmc_data         *data = host->data;
945

946
	if (data)
947 948
		dma_unmap_sg(&host->pdev->dev,
				data->sg, data->sg_len,
949
				mmc_get_dma_dir(data));
950 951
}

952 953 954 955 956 957
/*
 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
 * interrupt needed for both transfer directions.
 */
static void atmci_pdc_complete(struct atmel_mci *host)
958
{
959
	int transfer_size = host->data->blocks * host->data->blksz;
960
	int i;
961

962
	atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
963 964

	if ((!host->caps.has_rwproof)
965 966 967 968
	    && (host->data->flags & MMC_DATA_READ)) {
		if (host->caps.has_bad_data_ordering)
			for (i = 0; i < transfer_size; i++)
				host->buffer[i] = swab32(host->buffer[i]);
969 970
		sg_copy_from_buffer(host->data->sg, host->data->sg_len,
		                    host->buffer, transfer_size);
971
	}
972

973
	atmci_pdc_cleanup(host);
974

975 976 977
	dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
	atmci_set_pending(host, EVENT_XFER_COMPLETE);
	tasklet_schedule(&host->tasklet);
978 979
}

980 981 982 983 984 985 986
static void atmci_dma_cleanup(struct atmel_mci *host)
{
	struct mmc_data                 *data = host->data;

	if (data)
		dma_unmap_sg(host->dma.chan->device->dev,
				data->sg, data->sg_len,
987
				mmc_get_dma_dir(data));
988 989 990 991 992
}

/*
 * This function is called by the DMA driver from tasklet context.
 */
993 994 995 996 997 998 999
static void atmci_dma_complete(void *arg)
{
	struct atmel_mci	*host = arg;
	struct mmc_data		*data = host->data;

	dev_vdbg(&host->pdev->dev, "DMA complete\n");

1000
	if (host->caps.has_dma_conf_reg)
1001
		/* Disable DMA hardware handshaking on MCI */
1002
		atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
1003

1004 1005 1006 1007 1008 1009 1010
	atmci_dma_cleanup(host);

	/*
	 * If the card was removed, data will be NULL. No point trying
	 * to send the stop command or waiting for NBUSY in this case.
	 */
	if (data) {
1011 1012
		dev_dbg(&host->pdev->dev,
		        "(%s) set pending xfer complete\n", __func__);
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
		atmci_set_pending(host, EVENT_XFER_COMPLETE);
		tasklet_schedule(&host->tasklet);

		/*
		 * Regardless of what the documentation says, we have
		 * to wait for NOTBUSY even after block read
		 * operations.
		 *
		 * When the DMA transfer is complete, the controller
		 * may still be reading the CRC from the card, i.e.
		 * the data transfer is still in progress and we
		 * haven't seen all the potential error bits yet.
		 *
		 * The interrupt handler will schedule a different
		 * tasklet to finish things up when the data transfer
		 * is completely done.
		 *
		 * We may not complete the mmc request here anyway
		 * because the mmc layer may call back and cause us to
		 * violate the "don't submit new operations from the
		 * completion callback" rule of the dma engine
		 * framework.
		 */
1036
		atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1037 1038 1039
	}
}

1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
/*
 * Returns a mask of interrupt flags to be enabled after the whole
 * request has been prepared.
 */
static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
{
	u32 iflags;

	data->error = -EINPROGRESS;

	host->sg = data->sg;
1051
	host->sg_len = data->sg_len;
1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
	host->data = data;
	host->data_chan = NULL;

	iflags = ATMCI_DATA_ERROR_FLAGS;

	/*
	 * Errata: MMC data write operation with less than 12
	 * bytes is impossible.
	 *
	 * Errata: MCI Transmit Data Register (TDR) FIFO
	 * corruption when length is not multiple of 4.
	 */
	if (data->blocks * data->blksz < 12
			|| (data->blocks * data->blksz) & 3)
		host->need_reset = true;

	host->pio_offset = 0;
	if (data->flags & MMC_DATA_READ)
		iflags |= ATMCI_RXRDY;
	else
		iflags |= ATMCI_TXRDY;

	return iflags;
}

/*
 * Set interrupt flags and set block length into the MCI mode register even
 * if this value is also accessible in the MCI block register. It seems to be
 * necessary before the High Speed MCI version. It also map sg and configure
 * PDC registers.
 */
static u32
atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
{
	u32 iflags, tmp;
1087
	int i;
1088 1089 1090 1091 1092 1093 1094 1095 1096 1097

	data->error = -EINPROGRESS;

	host->data = data;
	host->sg = data->sg;
	iflags = ATMCI_DATA_ERROR_FLAGS;

	/* Enable pdc mode */
	atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);

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	if (data->flags & MMC_DATA_READ)
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		iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
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	else
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		iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
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	/* Set BLKLEN */
	tmp = atmci_readl(host, ATMCI_MR);
	tmp &= 0x0000ffff;
	tmp |= ATMCI_BLKLEN(data->blksz);
	atmci_writel(host, ATMCI_MR, tmp);

	/* Configure PDC */
	host->data_size = data->blocks * data->blksz;
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	dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
		   mmc_get_dma_dir(data));
1113 1114

	if ((!host->caps.has_rwproof)
1115
	    && (host->data->flags & MMC_DATA_WRITE)) {
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		sg_copy_to_buffer(host->data->sg, host->data->sg_len,
		                  host->buffer, host->data_size);
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		if (host->caps.has_bad_data_ordering)
			for (i = 0; i < host->data_size; i++)
				host->buffer[i] = swab32(host->buffer[i]);
	}
1122

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	if (host->data_size)
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		atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
				       XFER_RECEIVE : XFER_TRANSMIT);
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	return iflags;
}

static u32
1130
atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
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{
	struct dma_chan			*chan;
	struct dma_async_tx_descriptor	*desc;
	struct scatterlist		*sg;
	unsigned int			i;
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	enum dma_transfer_direction	slave_dirn;
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	unsigned int			sglen;
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	u32				maxburst;
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	u32 iflags;

	data->error = -EINPROGRESS;

	WARN_ON(host->data);
	host->sg = NULL;
	host->data = data;

	iflags = ATMCI_DATA_ERROR_FLAGS;
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	/*
	 * We don't do DMA on "complex" transfers, i.e. with
	 * non-word-aligned buffers or lengths. Also, we don't bother
	 * with all the DMA setup overhead for short transfers.
	 */
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	if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
		return atmci_prepare_data(host, data);
1156
	if (data->blksz & 3)
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		return atmci_prepare_data(host, data);
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	for_each_sg(data->sg, sg, data->sg_len, i) {
		if (sg->offset & 3 || sg->length & 3)
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			return atmci_prepare_data(host, data);
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	}

	/* If we don't have a channel, we can't do DMA */
	chan = host->dma.chan;
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	if (chan)
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		host->data_chan = chan;

	if (!chan)
		return -ENODEV;

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	if (data->flags & MMC_DATA_READ) {
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		host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
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		maxburst = atmci_convert_chksize(host,
						 host->dma_conf.src_maxburst);
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	} else {
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		host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
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		maxburst = atmci_convert_chksize(host,
						 host->dma_conf.dst_maxburst);
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	}
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	if (host->caps.has_dma_conf_reg)
		atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
			ATMCI_DMAEN);
1185

1186
	sglen = dma_map_sg(chan->device->dev, data->sg,
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			data->sg_len, mmc_get_dma_dir(data));
1188

1189
	dmaengine_slave_config(chan, &host->dma_conf);
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	desc = dmaengine_prep_slave_sg(chan,
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			data->sg, sglen, slave_dirn,
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			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!desc)
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		goto unmap_exit;
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	host->dma.data_desc = desc;
	desc->callback = atmci_dma_complete;
	desc->callback_param = host;

1200
	return iflags;
1201
unmap_exit:
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	dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
		     mmc_get_dma_dir(data));
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	return -ENOMEM;
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}

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static void
atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
{
	return;
}

/*
 * Start PDC according to transfer direction.
 */
static void
atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
{
	if (data->flags & MMC_DATA_READ)
		atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
	else
		atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
}

static void
atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
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{
	struct dma_chan			*chan = host->data_chan;
	struct dma_async_tx_descriptor	*desc = host->dma.data_desc;

	if (chan) {
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		dmaengine_submit(desc);
		dma_async_issue_pending(chan);
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	}
}

1237
static void atmci_stop_transfer(struct atmel_mci *host)
1238
{
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	dev_dbg(&host->pdev->dev,
	        "(%s) set pending xfer complete\n", __func__);
1241
	atmci_set_pending(host, EVENT_XFER_COMPLETE);
1242
	atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
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}

1245
/*
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Masanari Iida committed
1246
 * Stop data transfer because error(s) occurred.
1247
 */
1248
static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1249
{
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	atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
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}
1252

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static void atmci_stop_transfer_dma(struct atmel_mci *host)
{
	struct dma_chan *chan = host->data_chan;
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	if (chan) {
		dmaengine_terminate_all(chan);
		atmci_dma_cleanup(host);
	} else {
		/* Data transfer was stopped by the interrupt handler */
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		dev_dbg(&host->pdev->dev,
		        "(%s) set pending xfer complete\n", __func__);
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		atmci_set_pending(host, EVENT_XFER_COMPLETE);
		atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
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	}
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}

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/*
 * Start a request: prepare data if needed, prepare the command and activate
 * interrupts.
 */
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static void atmci_start_request(struct atmel_mci *host,
		struct atmel_mci_slot *slot)
1275
{
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	struct mmc_request	*mrq;
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	struct mmc_command	*cmd;
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	struct mmc_data		*data;
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	u32			iflags;
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	u32			cmdflags;
1281

1282 1283
	mrq = slot->mrq;
	host->cur_slot = slot;
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	host->mrq = mrq;
1285

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	host->pending_events = 0;
	host->completed_events = 0;
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	host->cmd_status = 0;
1289
	host->data_status = 0;
1290

1291 1292
	dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);

1293
	if (host->need_reset || host->caps.need_reset_after_xfer) {