pxa_camera.c 50.5 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14
/*
 * V4L2 Driver for PXA camera host
 *
 * Copyright (C) 2006, Sascha Hauer, Pengutronix
 * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
15
#include <linux/io.h>
16 17 18 19 20 21 22 23 24 25 26 27 28
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/moduleparam.h>
#include <linux/time.h>
#include <linux/version.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
29
#include <linux/sched.h>
30
#include <linux/slab.h>
31 32 33

#include <media/v4l2-common.h>
#include <media/v4l2-dev.h>
34
#include <media/videobuf-dma-sg.h>
35
#include <media/soc_camera.h>
36
#include <media/soc_mediabus.h>
37 38 39

#include <linux/videodev2.h>

40
#include <mach/dma.h>
41
#include <mach/camera.h>
42 43 44 45

#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
#define PXA_CAM_DRV_NAME "pxa27x-camera"

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
/* Camera Interface */
#define CICR0		0x0000
#define CICR1		0x0004
#define CICR2		0x0008
#define CICR3		0x000C
#define CICR4		0x0010
#define CISR		0x0014
#define CIFR		0x0018
#define CITOR		0x001C
#define CIBR0		0x0028
#define CIBR1		0x0030
#define CIBR2		0x0038

#define CICR0_DMAEN	(1 << 31)	/* DMA request enable */
#define CICR0_PAR_EN	(1 << 30)	/* Parity enable */
#define CICR0_SL_CAP_EN	(1 << 29)	/* Capture enable for slave mode */
#define CICR0_ENB	(1 << 28)	/* Camera interface enable */
#define CICR0_DIS	(1 << 27)	/* Camera interface disable */
#define CICR0_SIM	(0x7 << 24)	/* Sensor interface mode mask */
#define CICR0_TOM	(1 << 9)	/* Time-out mask */
#define CICR0_RDAVM	(1 << 8)	/* Receive-data-available mask */
#define CICR0_FEM	(1 << 7)	/* FIFO-empty mask */
#define CICR0_EOLM	(1 << 6)	/* End-of-line mask */
#define CICR0_PERRM	(1 << 5)	/* Parity-error mask */
#define CICR0_QDM	(1 << 4)	/* Quick-disable mask */
#define CICR0_CDM	(1 << 3)	/* Disable-done mask */
#define CICR0_SOFM	(1 << 2)	/* Start-of-frame mask */
#define CICR0_EOFM	(1 << 1)	/* End-of-frame mask */
#define CICR0_FOM	(1 << 0)	/* FIFO-overrun mask */

#define CICR1_TBIT	(1 << 31)	/* Transparency bit */
#define CICR1_RGBT_CONV	(0x3 << 29)	/* RGBT conversion mask */
#define CICR1_PPL	(0x7ff << 15)	/* Pixels per line mask */
#define CICR1_RGB_CONV	(0x7 << 12)	/* RGB conversion mask */
#define CICR1_RGB_F	(1 << 11)	/* RGB format */
#define CICR1_YCBCR_F	(1 << 10)	/* YCbCr format */
#define CICR1_RGB_BPP	(0x7 << 7)	/* RGB bis per pixel mask */
#define CICR1_RAW_BPP	(0x3 << 5)	/* Raw bis per pixel mask */
#define CICR1_COLOR_SP	(0x3 << 3)	/* Color space mask */
#define CICR1_DW	(0x7 << 0)	/* Data width mask */

#define CICR2_BLW	(0xff << 24)	/* Beginning-of-line pixel clock
					   wait count mask */
#define CICR2_ELW	(0xff << 16)	/* End-of-line pixel clock
					   wait count mask */
#define CICR2_HSW	(0x3f << 10)	/* Horizontal sync pulse width mask */
#define CICR2_BFPW	(0x3f << 3)	/* Beginning-of-frame pixel clock
					   wait count mask */
#define CICR2_FSW	(0x7 << 0)	/* Frame stabilization
					   wait count mask */

#define CICR3_BFW	(0xff << 24)	/* Beginning-of-frame line clock
					   wait count mask */
#define CICR3_EFW	(0xff << 16)	/* End-of-frame line clock
					   wait count mask */
#define CICR3_VSW	(0x3f << 10)	/* Vertical sync pulse width mask */
#define CICR3_BFPW	(0x3f << 3)	/* Beginning-of-frame pixel clock
					   wait count mask */
#define CICR3_LPF	(0x7ff << 0)	/* Lines per frame mask */

#define CICR4_MCLK_DLY	(0x3 << 24)	/* MCLK Data Capture Delay mask */
#define CICR4_PCLK_EN	(1 << 23)	/* Pixel clock enable */
#define CICR4_PCP	(1 << 22)	/* Pixel clock polarity */
#define CICR4_HSP	(1 << 21)	/* Horizontal sync polarity */
#define CICR4_VSP	(1 << 20)	/* Vertical sync polarity */
#define CICR4_MCLK_EN	(1 << 19)	/* MCLK enable */
#define CICR4_FR_RATE	(0x7 << 8)	/* Frame rate mask */
#define CICR4_DIV	(0xff << 0)	/* Clock divisor mask */

#define CISR_FTO	(1 << 15)	/* FIFO time-out */
#define CISR_RDAV_2	(1 << 14)	/* Channel 2 receive data available */
#define CISR_RDAV_1	(1 << 13)	/* Channel 1 receive data available */
#define CISR_RDAV_0	(1 << 12)	/* Channel 0 receive data available */
#define CISR_FEMPTY_2	(1 << 11)	/* Channel 2 FIFO empty */
#define CISR_FEMPTY_1	(1 << 10)	/* Channel 1 FIFO empty */
#define CISR_FEMPTY_0	(1 << 9)	/* Channel 0 FIFO empty */
#define CISR_EOL	(1 << 8)	/* End of line */
#define CISR_PAR_ERR	(1 << 7)	/* Parity error */
#define CISR_CQD	(1 << 6)	/* Camera interface quick disable */
#define CISR_CDD	(1 << 5)	/* Camera interface disable done */
#define CISR_SOF	(1 << 4)	/* Start of frame */
#define CISR_EOF	(1 << 3)	/* End of frame */
#define CISR_IFO_2	(1 << 2)	/* FIFO overrun for Channel 2 */
#define CISR_IFO_1	(1 << 1)	/* FIFO overrun for Channel 1 */
#define CISR_IFO_0	(1 << 0)	/* FIFO overrun for Channel 0 */

#define CIFR_FLVL2	(0x7f << 23)	/* FIFO 2 level mask */
#define CIFR_FLVL1	(0x7f << 16)	/* FIFO 1 level mask */
#define CIFR_FLVL0	(0xff << 8)	/* FIFO 0 level mask */
#define CIFR_THL_0	(0x3 << 4)	/* Threshold Level for Channel 0 FIFO */
#define CIFR_RESET_F	(1 << 3)	/* Reset input FIFOs */
#define CIFR_FEN2	(1 << 2)	/* FIFO enable for channel 2 */
#define CIFR_FEN1	(1 << 1)	/* FIFO enable for channel 1 */
#define CIFR_FEN0	(1 << 0)	/* FIFO enable for channel 0 */

141 142 143 144 145 146 147 148
#define CICR0_SIM_MP	(0 << 24)
#define CICR0_SIM_SP	(1 << 24)
#define CICR0_SIM_MS	(2 << 24)
#define CICR0_SIM_EP	(3 << 24)
#define CICR0_SIM_ES	(4 << 24)

#define CICR1_DW_VAL(x)   ((x) & CICR1_DW)	    /* Data bus width */
#define CICR1_PPL_VAL(x)  (((x) << 15) & CICR1_PPL) /* Pixels per line */
149 150 151
#define CICR1_COLOR_SP_VAL(x)	(((x) << 3) & CICR1_COLOR_SP)	/* color space */
#define CICR1_RGB_BPP_VAL(x)	(((x) << 7) & CICR1_RGB_BPP)	/* bpp for rgb */
#define CICR1_RGBT_CONV_VAL(x)	(((x) << 29) & CICR1_RGBT_CONV)	/* rgbt conv */
152 153 154 155 156 157 158 159 160 161 162 163

#define CICR2_BLW_VAL(x)  (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
#define CICR2_ELW_VAL(x)  (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
#define CICR2_HSW_VAL(x)  (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
#define CICR2_FSW_VAL(x)  (((x) << 0) & CICR2_FSW)  /* Frame stabilization wait count */

#define CICR3_BFW_VAL(x)  (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count  */
#define CICR3_EFW_VAL(x)  (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
#define CICR3_VSW_VAL(x)  (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
#define CICR3_LPF_VAL(x)  (((x) << 0) & CICR3_LPF)  /* Lines per frame */

164 165 166 167 168 169 170
#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
			CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
			CICR0_EOFM | CICR0_FOM)

/*
 * Structures
 */
171 172 173 174 175 176 177 178 179 180 181 182 183
enum pxa_camera_active_dma {
	DMA_Y = 0x1,
	DMA_U = 0x2,
	DMA_V = 0x4,
};

/* descriptor needed for the PXA DMA engine */
struct pxa_cam_dma {
	dma_addr_t		sg_dma;
	struct pxa_dma_desc	*sg_cpu;
	size_t			sg_size;
	int			sglen;
};
184 185 186 187

/* buffer for one video frame */
struct pxa_buffer {
	/* common v4l buffer stuff -- must be first */
188 189
	struct videobuf_buffer		vb;
	enum v4l2_mbus_pixelcode	code;
190
	/* our descriptor lists for Y, U and V channels */
191 192 193
	struct pxa_cam_dma		dmas[3];
	int				inwork;
	enum pxa_camera_active_dma	active_dma;
194 195 196
};

struct pxa_camera_dev {
197
	struct soc_camera_host	soc_host;
198 199
	/*
	 * PXA27x is only supposed to handle one camera on its Quick Capture
200
	 * interface. If anyone ever builds hardware to enable more than
201 202
	 * one camera, they will have to modify this driver too
	 */
203 204 205 206 207
	struct soc_camera_device *icd;
	struct clk		*clk;

	unsigned int		irq;
	void __iomem		*base;
208

209
	int			channels;
210
	unsigned int		dma_chans[3];
211 212 213 214

	struct pxacamera_platform_data *pdata;
	struct resource		*res;
	unsigned long		platform_flags;
215 216 217
	unsigned long		ciclk;
	unsigned long		mclk;
	u32			mclk_divisor;
218 219 220 221 222 223

	struct list_head	capture;

	spinlock_t		lock;

	struct pxa_buffer	*active;
224
	struct pxa_dma_desc	*sg_tail[3];
225 226

	u32			save_cicr[5];
227 228
};

229 230 231 232
struct pxa_cam {
	unsigned long flags;
};

233 234 235 236 237 238 239
static const char *pxa_cam_driver_description = "PXA_Camera";

static unsigned int vid_limit = 16;	/* Video memory limit, in Mb */

/*
 *  Videobuf operations
 */
240 241
static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
			      unsigned int *size)
242 243
{
	struct soc_camera_device *icd = vq->priv_data;
244 245 246 247 248
	int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
						icd->current_fmt->host_fmt);

	if (bytes_per_line < 0)
		return bytes_per_line;
249

250
	dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size);
251

252
	*size = bytes_per_line * icd->user_height;
253 254 255 256 257 258 259 260 261 262 263 264

	if (0 == *count)
		*count = 32;
	while (*size * *count > vid_limit * 1024 * 1024)
		(*count)--;

	return 0;
}

static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
{
	struct soc_camera_device *icd = vq->priv_data;
265
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
266
	struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
267
	int i;
268 269 270

	BUG_ON(in_interrupt());

271
	dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
272 273
		&buf->vb, buf->vb.baddr, buf->vb.bsize);

274 275 276 277
	/*
	 * This waits until this buffer is out of danger, i.e., until it is no
	 * longer in STATE_QUEUED or STATE_ACTIVE
	 */
278 279 280 281
	videobuf_waiton(&buf->vb, 0, 0);
	videobuf_dma_unmap(vq, dma);
	videobuf_dma_free(dma);

282 283
	for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
		if (buf->dmas[i].sg_cpu)
284 285
			dma_free_coherent(ici->v4l2_dev.dev,
					  buf->dmas[i].sg_size,
286 287 288 289
					  buf->dmas[i].sg_cpu,
					  buf->dmas[i].sg_dma);
		buf->dmas[i].sg_cpu = NULL;
	}
290 291 292 293

	buf->vb.state = VIDEOBUF_NEEDS_INIT;
}

294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332
static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
			       int sg_first_ofs, int size)
{
	int i, offset, dma_len, xfer_len;
	struct scatterlist *sg;

	offset = sg_first_ofs;
	for_each_sg(sglist, sg, sglen, i) {
		dma_len = sg_dma_len(sg);

		/* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
		xfer_len = roundup(min(dma_len - offset, size), 8);

		size = max(0, size - xfer_len);
		offset = 0;
		if (size == 0)
			break;
	}

	BUG_ON(size != 0);
	return i + 1;
}

/**
 * pxa_init_dma_channel - init dma descriptors
 * @pcdev: pxa camera device
 * @buf: pxa buffer to find pxa dma channel
 * @dma: dma video buffer
 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
 * @cibr: camera Receive Buffer Register
 * @size: bytes to transfer
 * @sg_first: first element of sg_list
 * @sg_first_ofs: offset in first element of sg_list
 *
 * Prepares the pxa dma descriptors to transfer one camera channel.
 * Beware sg_first and sg_first_ofs are both input and output parameters.
 *
 * Returns 0 or -ENOMEM if no coherent memory is available
 */
333 334 335
static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
				struct pxa_buffer *buf,
				struct videobuf_dmabuf *dma, int channel,
336 337
				int cibr, int size,
				struct scatterlist **sg_first, int *sg_first_ofs)
338 339
{
	struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
340
	struct device *dev = pcdev->soc_host.v4l2_dev.dev;
341 342 343
	struct scatterlist *sg;
	int i, offset, sglen;
	int dma_len = 0, xfer_len = 0;
344 345

	if (pxa_dma->sg_cpu)
346
		dma_free_coherent(dev, pxa_dma->sg_size,
347 348
				  pxa_dma->sg_cpu, pxa_dma->sg_dma);

349 350 351
	sglen = calculate_dma_sglen(*sg_first, dma->sglen,
				    *sg_first_ofs, size);

352
	pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
353
	pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
354 355 356 357 358
					     &pxa_dma->sg_dma, GFP_KERNEL);
	if (!pxa_dma->sg_cpu)
		return -ENOMEM;

	pxa_dma->sglen = sglen;
359
	offset = *sg_first_ofs;
360

361
	dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
362
		*sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
363

364 365 366

	for_each_sg(*sg_first, sg, sglen, i) {
		dma_len = sg_dma_len(sg);
367 368

		/* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
369
		xfer_len = roundup(min(dma_len - offset, size), 8);
370

371 372 373 374
		size = max(0, size - xfer_len);

		pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
		pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
375 376
		pxa_dma->sg_cpu[i].dcmd =
			DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
377 378 379 380
#ifdef DEBUG
		if (!i)
			pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
#endif
381 382
		pxa_dma->sg_cpu[i].ddadr =
			pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
383

384
		dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
385 386 387 388 389 390
			 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
			 sg_dma_address(sg) + offset, xfer_len);
		offset = 0;

		if (size == 0)
			break;
391 392
	}

393 394
	pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
	pxa_dma->sg_cpu[sglen].dcmd  = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
395

396 397 398 399 400 401 402 403 404 405 406 407 408 409 410
	/*
	 * Handle 1 special case :
	 *  - in 3 planes (YUV422P format), we might finish with xfer_len equal
	 *    to dma_len (end on PAGE boundary). In this case, the sg element
	 *    for next plane should be the next after the last used to store the
	 *    last scatter gather RAM page
	 */
	if (xfer_len >= dma_len) {
		*sg_first_ofs = xfer_len - dma_len;
		*sg_first = sg_next(sg);
	} else {
		*sg_first_ofs = xfer_len;
		*sg_first = sg;
	}

411 412 413
	return 0;
}

414 415 416 417 418 419 420 421 422 423 424 425 426 427
static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
				    struct pxa_buffer *buf)
{
	buf->active_dma = DMA_Y;
	if (pcdev->channels == 3)
		buf->active_dma |= DMA_U | DMA_V;
}

/*
 * Please check the DMA prepared buffer structure in :
 *   Documentation/video4linux/pxa_camera.txt
 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
 * modification while DMA chain is running will work anyway.
 */
428 429
static int pxa_videobuf_prepare(struct videobuf_queue *vq,
		struct videobuf_buffer *vb, enum v4l2_field field)
430 431
{
	struct soc_camera_device *icd = vq->priv_data;
432
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
433
	struct pxa_camera_dev *pcdev = ici->priv;
434
	struct device *dev = pcdev->soc_host.v4l2_dev.dev;
435
	struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
436 437
	int ret;
	int size_y, size_u = 0, size_v = 0;
438 439 440 441 442
	int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
						icd->current_fmt->host_fmt);

	if (bytes_per_line < 0)
		return bytes_per_line;
443

444
	dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
445 446 447 448 449 450
		vb, vb->baddr, vb->bsize);

	/* Added list head initialization on alloc */
	WARN_ON(!list_empty(&vb->queue));

#ifdef DEBUG
451 452 453 454
	/*
	 * This can be useful if you want to see if we actually fill
	 * the buffer with something
	 */
455 456 457 458 459
	memset((void *)vb->baddr, 0xaa, vb->bsize);
#endif

	BUG_ON(NULL == icd->current_fmt);

460 461 462 463
	/*
	 * I think, in buf_prepare you only have to protect global data,
	 * the actual buffer is yours
	 */
464 465
	buf->inwork = 1;

466
	if (buf->code	!= icd->current_fmt->code ||
467 468
	    vb->width	!= icd->user_width ||
	    vb->height	!= icd->user_height ||
469
	    vb->field	!= field) {
470
		buf->code	= icd->current_fmt->code;
471 472
		vb->width	= icd->user_width;
		vb->height	= icd->user_height;
473 474 475 476
		vb->field	= field;
		vb->state	= VIDEOBUF_NEEDS_INIT;
	}

477
	vb->size = bytes_per_line * vb->height;
478 479 480 481 482 483
	if (0 != vb->baddr && vb->bsize < vb->size) {
		ret = -EINVAL;
		goto out;
	}

	if (vb->state == VIDEOBUF_NEEDS_INIT) {
484 485
		int size = vb->size;
		int next_ofs = 0;
486
		struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
487
		struct scatterlist *sg;
488 489 490 491 492

		ret = videobuf_iolock(vq, vb, NULL);
		if (ret)
			goto fail;

493
		if (pcdev->channels == 3) {
494 495 496 497 498 499
			size_y = size / 2;
			size_u = size_v = size / 4;
		} else {
			size_y = size;
		}

500
		sg = dma->sglist;
501

502 503 504
		/* init DMA for Y channel */
		ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
					   &sg, &next_ofs);
505
		if (ret) {
506
			dev_err(dev, "DMA initialization for Y/RGB failed\n");
507 508 509
			goto fail;
		}

510 511 512 513 514
		/* init DMA for U channel */
		if (size_u)
			ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
						   size_u, &sg, &next_ofs);
		if (ret) {
515
			dev_err(dev, "DMA initialization for U failed\n");
516 517 518 519 520 521 522 523
			goto fail_u;
		}

		/* init DMA for V channel */
		if (size_v)
			ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
						   size_v, &sg, &next_ofs);
		if (ret) {
524
			dev_err(dev, "DMA initialization for V failed\n");
525
			goto fail_v;
526 527 528 529 530 531
		}

		vb->state = VIDEOBUF_PREPARED;
	}

	buf->inwork = 0;
532
	pxa_videobuf_set_actdma(pcdev, buf);
533 534 535

	return 0;

536
fail_v:
537
	dma_free_coherent(dev, buf->dmas[1].sg_size,
538 539
			  buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
fail_u:
540
	dma_free_coherent(dev, buf->dmas[0].sg_size,
541
			  buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
542 543 544 545 546 547 548
fail:
	free_buffer(vq, buf);
out:
	buf->inwork = 0;
	return ret;
}

549 550 551 552 553 554 555 556 557 558 559 560 561 562 563
/**
 * pxa_dma_start_channels - start DMA channel for active buffer
 * @pcdev: pxa camera device
 *
 * Initialize DMA channels to the beginning of the active video buffer, and
 * start these channels.
 */
static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
{
	int i;
	struct pxa_buffer *active;

	active = pcdev->active;

	for (i = 0; i < pcdev->channels; i++) {
564 565
		dev_dbg(pcdev->soc_host.v4l2_dev.dev,
			"%s (channel=%d) ddadr=%08x\n", __func__,
566 567 568 569 570 571 572 573 574 575 576
			i, active->dmas[i].sg_dma);
		DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
		DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
	}
}

static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
{
	int i;

	for (i = 0; i < pcdev->channels; i++) {
577 578
		dev_dbg(pcdev->soc_host.v4l2_dev.dev,
			"%s (channel=%d)\n", __func__, i);
579 580 581 582 583 584 585 586 587 588 589 590 591 592
		DCSR(pcdev->dma_chans[i]) = 0;
	}
}

static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
				 struct pxa_buffer *buf)
{
	int i;
	struct pxa_dma_desc *buf_last_desc;

	for (i = 0; i < pcdev->channels; i++) {
		buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
		buf_last_desc->ddadr = DDADR_STOP;

593 594 595
		if (pcdev->sg_tail[i])
			/* Link the new buffer to the old tail */
			pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
596

597 598 599
		/* Update the channel tail */
		pcdev->sg_tail[i] = buf_last_desc;
	}
600 601 602 603 604 605 606 607 608 609 610 611
}

/**
 * pxa_camera_start_capture - start video capturing
 * @pcdev: camera device
 *
 * Launch capturing. DMA channels should not be active yet. They should get
 * activated at the end of frame interrupt, to capture only whole frames, and
 * never begin the capture of a partial frame.
 */
static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
{
612
	unsigned long cicr0;
613

614
	dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
615 616 617 618 619 620 621 622 623 624 625 626 627 628 629
	/* Enable End-Of-Frame Interrupt */
	cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
	cicr0 &= ~CICR0_EOFM;
	__raw_writel(cicr0, pcdev->base + CICR0);
}

static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
{
	unsigned long cicr0;

	pxa_dma_stop_channels(pcdev);

	cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
	__raw_writel(cicr0, pcdev->base + CICR0);

630
	pcdev->active = NULL;
631
	dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
632 633
}

634
/* Called under spinlock_irqsave(&pcdev->lock, ...) */
635 636
static void pxa_videobuf_queue(struct videobuf_queue *vq,
			       struct videobuf_buffer *vb)
637 638
{
	struct soc_camera_device *icd = vq->priv_data;
639
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
640 641 642
	struct pxa_camera_dev *pcdev = ici->priv;
	struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);

643 644
	dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
		__func__, vb, vb->baddr, vb->bsize, pcdev->active);
645

646 647 648
	list_add_tail(&vb->queue, &pcdev->capture);

	vb->state = VIDEOBUF_ACTIVE;
649
	pxa_dma_add_tail_buf(pcdev, buf);
650

651 652
	if (!pcdev->active)
		pxa_camera_start_capture(pcdev);
653 654 655 656 657 658 659 660
}

static void pxa_videobuf_release(struct videobuf_queue *vq,
				 struct videobuf_buffer *vb)
{
	struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
#ifdef DEBUG
	struct soc_camera_device *icd = vq->priv_data;
661
	struct device *dev = icd->dev.parent;
662

663
	dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
664 665 666 667
		vb, vb->baddr, vb->bsize);

	switch (vb->state) {
	case VIDEOBUF_ACTIVE:
668
		dev_dbg(dev, "%s (active)\n", __func__);
669 670
		break;
	case VIDEOBUF_QUEUED:
671
		dev_dbg(dev, "%s (queued)\n", __func__);
672 673
		break;
	case VIDEOBUF_PREPARED:
674
		dev_dbg(dev, "%s (prepared)\n", __func__);
675 676
		break;
	default:
677
		dev_dbg(dev, "%s (unknown)\n", __func__);
678 679 680 681 682 683 684
		break;
	}
#endif

	free_buffer(vq, buf);
}

685 686 687 688
static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
			      struct videobuf_buffer *vb,
			      struct pxa_buffer *buf)
{
689
	int i;
690

691 692 693 694 695 696
	/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
	list_del_init(&vb->queue);
	vb->state = VIDEOBUF_DONE;
	do_gettimeofday(&vb->ts);
	vb->field_count++;
	wake_up(&vb->done);
697 698
	dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
		__func__, vb);
699 700

	if (list_empty(&pcdev->capture)) {
701 702 703
		pxa_camera_stop_capture(pcdev);
		for (i = 0; i < pcdev->channels; i++)
			pcdev->sg_tail[i] = NULL;
704 705 706 707 708 709 710
		return;
	}

	pcdev->active = list_entry(pcdev->capture.next,
				   struct pxa_buffer, vb.queue);
}

711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733
/**
 * pxa_camera_check_link_miss - check missed DMA linking
 * @pcdev: camera device
 *
 * The DMA chaining is done with DMA running. This means a tiny temporal window
 * remains, where a buffer is queued on the chain, while the chain is already
 * stopped. This means the tailed buffer would never be transfered by DMA.
 * This function restarts the capture for this corner case, where :
 *  - DADR() == DADDR_STOP
 *  - a videobuffer is queued on the pcdev->capture list
 *
 * Please check the "DMA hot chaining timeslice issue" in
 *   Documentation/video4linux/pxa_camera.txt
 *
 * Context: should only be called within the dma irq handler
 */
static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
{
	int i, is_dma_stopped = 1;

	for (i = 0; i < pcdev->channels; i++)
		if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
			is_dma_stopped = 0;
734 735
	dev_dbg(pcdev->soc_host.v4l2_dev.dev,
		"%s : top queued buffer=%p, dma_stopped=%d\n",
736 737 738 739 740
		__func__, pcdev->active, is_dma_stopped);
	if (pcdev->active && is_dma_stopped)
		pxa_camera_start_capture(pcdev);
}

741 742
static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
			       enum pxa_camera_active_dma act_dma)
743
{
744
	struct device *dev = pcdev->soc_host.v4l2_dev.dev;
745 746
	struct pxa_buffer *buf;
	unsigned long flags;
747
	u32 status, camera_status, overrun;
748 749 750 751
	struct videobuf_buffer *vb;

	spin_lock_irqsave(&pcdev->lock, flags);

752
	status = DCSR(channel);
753 754 755 756 757 758
	DCSR(channel) = status;

	camera_status = __raw_readl(pcdev->base + CISR);
	overrun = CISR_IFO_0;
	if (pcdev->channels == 3)
		overrun |= CISR_IFO_1 | CISR_IFO_2;
759

760
	if (status & DCSR_BUSERR) {
761
		dev_err(dev, "DMA Bus Error IRQ!\n");
762 763 764
		goto out;
	}

765
	if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
766 767
		dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
			status);
768 769 770
		goto out;
	}

771 772 773 774 775 776 777 778 779 780 781 782 783
	/*
	 * pcdev->active should not be NULL in DMA irq handler.
	 *
	 * But there is one corner case : if capture was stopped due to an
	 * overrun of channel 1, and at that same channel 2 was completed.
	 *
	 * When handling the overrun in DMA irq for channel 1, we'll stop the
	 * capture and restart it (and thus set pcdev->active to NULL). But the
	 * DMA irq handler will already be pending for channel 2. So on entering
	 * the DMA irq handler for channel 2 there will be no active buffer, yet
	 * that is normal.
	 */
	if (!pcdev->active)
784 785 786 787 788 789
		goto out;

	vb = &pcdev->active->vb;
	buf = container_of(vb, struct pxa_buffer, vb);
	WARN_ON(buf->inwork || list_empty(&vb->queue));

790
	dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
791 792 793 794
		__func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
		status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));

	if (status & DCSR_ENDINTR) {
795 796 797 798 799 800
		/*
		 * It's normal if the last frame creates an overrun, as there
		 * are no more DMA descriptors to fetch from QCI fifos
		 */
		if (camera_status & overrun &&
		    !list_is_last(pcdev->capture.next, &pcdev->capture)) {
801
			dev_dbg(dev, "FIFO overrun! CISR: %x\n",
802 803 804 805 806 807 808 809 810 811 812
				camera_status);
			pxa_camera_stop_capture(pcdev);
			pxa_camera_start_capture(pcdev);
			goto out;
		}
		buf->active_dma &= ~act_dma;
		if (!buf->active_dma) {
			pxa_camera_wakeup(pcdev, vb, buf);
			pxa_camera_check_link_miss(pcdev);
		}
	}
813 814 815 816 817

out:
	spin_unlock_irqrestore(&pcdev->lock, flags);
}

818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835
static void pxa_camera_dma_irq_y(int channel, void *data)
{
	struct pxa_camera_dev *pcdev = data;
	pxa_camera_dma_irq(channel, pcdev, DMA_Y);
}

static void pxa_camera_dma_irq_u(int channel, void *data)
{
	struct pxa_camera_dev *pcdev = data;
	pxa_camera_dma_irq(channel, pcdev, DMA_U);
}

static void pxa_camera_dma_irq_v(int channel, void *data)
{
	struct pxa_camera_dev *pcdev = data;
	pxa_camera_dma_irq(channel, pcdev, DMA_V);
}

836
static struct videobuf_queue_ops pxa_videobuf_ops = {
837 838 839 840 841 842
	.buf_setup      = pxa_videobuf_setup,
	.buf_prepare    = pxa_videobuf_prepare,
	.buf_queue      = pxa_videobuf_queue,
	.buf_release    = pxa_videobuf_release,
};

843
static void pxa_camera_init_videobuf(struct videobuf_queue *q,
844 845
			      struct soc_camera_device *icd)
{
846 847 848
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
	struct pxa_camera_dev *pcdev = ici->priv;

849 850 851 852
	/*
	 * We must pass NULL as dev pointer, then all pci_* dma operations
	 * transform to normal dma_* ones.
	 */
853
	videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
854 855 856 857
				V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
				sizeof(struct pxa_buffer), icd);
}

858 859
static u32 mclk_get_divisor(struct platform_device *pdev,
			    struct pxa_camera_dev *pcdev)
860
{
861
	unsigned long mclk = pcdev->mclk;
862
	struct device *dev = &pdev->dev;
863
	u32 div;
864 865
	unsigned long lcdclk;

866 867
	lcdclk = clk_get_rate(pcdev->clk);
	pcdev->ciclk = lcdclk;
868

869 870 871
	/* mclk <= ciclk / 4 (27.4.2) */
	if (mclk > lcdclk / 4) {
		mclk = lcdclk / 4;
872
		dev_warn(dev, "Limiting master clock to %lu\n", mclk);
873 874 875 876
	}

	/* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
	div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
877

878 879 880
	/* If we're not supplying MCLK, leave it at 0 */
	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
		pcdev->mclk = lcdclk / (2 * (div + 1));
881

882
	dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
883
		lcdclk, mclk, div);
884 885 886 887

	return div;
}

888 889 890 891 892 893 894 895 896
static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
				     unsigned long pclk)
{
	/* We want a timeout > 1 pixel time, not ">=" */
	u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;

	__raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
}

897
static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
898 899 900
{
	u32 cicr4 = 0;

901 902
	/* disable all interrupts */
	__raw_writel(0x3ff, pcdev->base + CICR0);
903 904 905 906 907 908 909 910 911 912 913 914

	if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
		cicr4 |= CICR4_PCLK_EN;
	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
		cicr4 |= CICR4_MCLK_EN;
	if (pcdev->platform_flags & PXA_CAMERA_PCP)
		cicr4 |= CICR4_PCP;
	if (pcdev->platform_flags & PXA_CAMERA_HSP)
		cicr4 |= CICR4_HSP;
	if (pcdev->platform_flags & PXA_CAMERA_VSP)
		cicr4 |= CICR4_VSP;

915 916 917 918 919 920 921 922
	__raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);

	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
		/* Initialise the timeout under the assumption pclk = mclk */
		recalculate_fifo_timeout(pcdev, pcdev->mclk);
	else
		/* "Safe default" - 13MHz */
		recalculate_fifo_timeout(pcdev, 13000000);
923 924 925 926

	clk_enable(pcdev->clk);
}

927
static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
928 929 930 931 932 933 934
{
	clk_disable(pcdev->clk);
}

static irqreturn_t pxa_camera_irq(int irq, void *data)
{
	struct pxa_camera_dev *pcdev = data;
935
	unsigned long status, cifr, cicr0;
936 937
	struct pxa_buffer *buf;
	struct videobuf_buffer *vb;
938

939
	status = __raw_readl(pcdev->base + CISR);
940 941
	dev_dbg(pcdev->soc_host.v4l2_dev.dev,
		"Camera interrupt status 0x%lx\n", status);
942

943 944 945
	if (!status)
		return IRQ_NONE;

946
	__raw_writel(status, pcdev->base + CISR);
947 948

	if (status & CISR_EOF) {
949 950 951 952
		/* Reset the FIFOs */
		cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
		__raw_writel(cifr, pcdev->base + CIFR);

953 954 955 956 957 958 959 960
		pcdev->active = list_first_entry(&pcdev->capture,
					   struct pxa_buffer, vb.queue);
		vb = &pcdev->active->vb;
		buf = container_of(vb, struct pxa_buffer, vb);
		pxa_videobuf_set_actdma(pcdev, buf);

		pxa_dma_start_channels(pcdev);

961 962
		cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
		__raw_writel(cicr0, pcdev->base + CICR0);
963 964
	}

965 966 967
	return IRQ_HANDLED;
}

968 969 970 971 972
/*
 * The following two functions absolutely depend on the fact, that
 * there can be only one camera on PXA quick capture interface
 * Called with .video_lock held
 */
973
static int pxa_camera_add_device(struct soc_camera_device *icd)
974 975 976 977
{
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
	struct pxa_camera_dev *pcdev = ici->priv;

978 979
	if (pcdev->icd)
		return -EBUSY;
980

981
	pxa_camera_activate(pcdev);
982 983

	pcdev->icd = icd;
984

985
	dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n",
986
		 icd->devnum);
987

988
	return 0;
989 990
}

991
/* Called with .video_lock held */
992
static void pxa_camera_remove_device(struct soc_camera_device *icd)
993 994 995 996 997 998
{
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
	struct pxa_camera_dev *pcdev = ici->priv;

	BUG_ON(icd != pcdev->icd);

999
	dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n",
1000 1001 1002
		 icd->devnum);

	/* disable capture, disable interrupts */
1003
	__raw_writel(0x3ff, pcdev->base + CICR0);
1004

1005
	/* Stop DMA engine */
1006 1007 1008
	DCSR(pcdev->dma_chans[0]) = 0;
	DCSR(pcdev->dma_chans[1]) = 0;
	DCSR(pcdev->dma_chans[2]) = 0;
1009

1010
	pxa_camera_deactivate(pcdev);
1011 1012 1013 1014

	pcdev->icd = NULL;
}

1015 1016
static int test_platform_param(struct pxa_camera_dev *pcdev,
			       unsigned char buswidth, unsigned long *flags)
1017
{
1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028
	/*
	 * Platform specified synchronization and pixel clock polarities are
	 * only a recommendation and are only used during probing. The PXA270
	 * quick capture interface supports both.
	 */
	*flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
		  SOCAM_MASTER : SOCAM_SLAVE) |
		SOCAM_HSYNC_ACTIVE_HIGH |
		SOCAM_HSYNC_ACTIVE_LOW |
		SOCAM_VSYNC_ACTIVE_HIGH |
		SOCAM_VSYNC_ACTIVE_LOW |
1029
		SOCAM_DATA_ACTIVE_HIGH |
1030 1031
		SOCAM_PCLK_SAMPLE_RISING |
		SOCAM_PCLK_SAMPLE_FALLING;
1032 1033

	/* If requested data width is supported by the platform, use it */
1034
	switch (buswidth) {
1035
	case 10:
1036 1037 1038
		if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
			return -EINVAL;
		*flags |= SOCAM_DATAWIDTH_10;
1039 1040
		break;
	case 9:
1041 1042 1043
		if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
			return -EINVAL;
		*flags |= SOCAM_DATAWIDTH_9;
1044 1045
		break;
	case 8:
1046 1047 1048
		if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
			return -EINVAL;
		*flags |= SOCAM_DATAWIDTH_8;
1049 1050 1051
		break;
	default:
		return -EINVAL;
1052
	}
1053 1054 1055 1056

	return 0;
}

1057 1058
static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
				  unsigned long flags, __u32 pixfmt)
1059
{
1060
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1061
	struct pxa_camera_dev *pcdev = ici->priv;
1062
	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1063
	unsigned long dw, bpp;
1064 1065 1066 1067 1068
	u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
	int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top);

	if (ret < 0)
		y_skip_top = 0;
1069

1070 1071 1072 1073
	/*
	 * Datawidth is now guaranteed to be equal to one of the three values.
	 * We fix bit-per-pixel equal to data-width...
	 */
1074
	switch (flags & SOCAM_DATAWIDTH_MASK) {
1075
	case SOCAM_DATAWIDTH_10:
1076 1077 1078
		dw = 4;
		bpp = 0x40;
		break;
1079
	case SOCAM_DATAWIDTH_9:
1080 1081 1082 1083
		dw = 3;
		bpp = 0x20;
		break;
	default:
1084 1085 1086 1087
		/*
		 * Actually it can only be 8 now,
		 * default is just to silence compiler warnings
		 */
1088
	case SOCAM_DATAWIDTH_8:
1089 1090 1091 1092 1093 1094 1095 1096
		dw = 2;
		bpp = 0;
	}

	if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
		cicr4 |= CICR4_PCLK_EN;
	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
		cicr4 |= CICR4_MCLK_EN;
1097
	if (flags & SOCAM_PCLK_SAMPLE_FALLING)
1098
		cicr4 |= CICR4_PCP;
1099
	if (flags & SOCAM_HSYNC_ACTIVE_LOW)
1100
		cicr4 |= CICR4_HSP;
1101
	if (flags & SOCAM_VSYNC_ACTIVE_LOW)
1102 1103
		cicr4 |= CICR4_VSP;

1104
	cicr0 = __raw_readl(pcdev->base + CICR0);
1105
	if (cicr0 & CICR0_ENB)
1106
		__raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1107

1108
	cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1109 1110 1111

	switch (pixfmt) {
	case V4L2_PIX_FMT_YUV422P:
1112
		pcdev->channels = 3;
1113
		cicr1 |= CICR1_YCBCR_F;
1114 1115 1116 1117 1118 1119 1120 1121 1122
		/*
		 * Normally, pxa bus wants as input UYVY format. We allow all
		 * reorderings of the YUV422 format, as no processing is done,
		 * and the YUV stream is just passed through without any
		 * transformation. Note that UYVY is the only format that
		 * should be used if pxa framebuffer Overlay2 is used.
		 */
	case V4L2_PIX_FMT_UYVY:
	case V4L2_PIX_FMT_VYUY:
1123
	case V4L2_PIX_FMT_YUYV:
1124
	case V4L2_PIX_FMT_YVYU:
1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135
		cicr1 |= CICR1_COLOR_SP_VAL(2);
		break;
	case V4L2_PIX_FMT_RGB555:
		cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
			CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
		break;
	case V4L2_PIX_FMT_RGB565:
		cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
		break;
	}

1136
	cicr2 = 0;
1137
	cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1138
		CICR3_BFW_VAL(min((u32)255, y_skip_top));
1139
	cicr4 |= pcdev->mclk_divisor;
1140 1141 1142 1143 1144

	__raw_writel(cicr1, pcdev->base + CICR1);
	__raw_writel(cicr2, pcdev->base + CICR2);
	__raw_writel(cicr3, pcdev->base + CICR3);
	__raw_writel(cicr4, pcdev->base + CICR4);
1145 1146

	/* CIF interrupts are not used, only DMA */
1147 1148 1149 1150
	cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
		CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
	cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
	__raw_writel(cicr0, pcdev->base + CICR0);
1151 1152 1153 1154 1155 1156 1157
}

static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
{
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
	struct pxa_camera_dev *pcdev = ici->priv;
	unsigned long bus_flags, camera_flags, common_flags;
1158 1159
	const struct soc_mbus_pixelfmt *fmt;
	int ret;
1160 1161
	struct pxa_cam *cam = icd->host_priv;

1162 1163 1164 1165 1166
	fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
	if (!fmt)
		return -EINVAL;

	ret = test_platform_param(pcdev, fmt->bits_per_sample, &bus_flags);
1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
	if (ret < 0)
		return ret;

	camera_flags = icd->ops->query_bus_param(icd);

	common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
	if (!common_flags)
		return -EINVAL;

	pcdev->channels = 1;

	/* Make choises, based on platform preferences */
	if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
	    (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
		if (pcdev->platform_flags & PXA_CAMERA_HSP)
			common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
		else
			common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
	}

	if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
	    (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
		if (pcdev->platform_flags & PXA_CAMERA_VSP)
			common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
		else
			common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
	}

	if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
	    (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
		if (pcdev->platform_flags & PXA_CAMERA_PCP)
			common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
		else
			common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
	}

	cam->flags = common_flags;

	ret = icd->ops->set_bus_param(icd, common_flags);
	if (ret < 0)
		return ret;

	pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1210 1211 1212 1213

	return 0;
}

1214 1215
static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
				    unsigned char buswidth)
1216
{
1217
	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1218 1219
	struct pxa_camera_dev *pcdev = ici->priv;
	unsigned long bus_flags, camera_flags;
1220
	int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1221 1222 1223 1224 1225 1226 1227 1228 1229

	if (ret < 0)
		return ret;

	camera_flags = icd->ops->query_bus_param(icd);

	return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
}

1230
static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
1231
	{
1232 1233 1234 1235 1236
		.fourcc			= V4L2_PIX_FMT_YUV422P,
		.name			= "Planar YUV422 16 bit",
		.bits_per_sample	= 8,
		.packing		= SOC_MBUS_PACKING_2X8_PADHI,
		.order			= SOC_MBUS_ORDER_LE,
1237 1238 1239
	},
};

1240 1241
/* This will be corrected as we get more formats */
static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
1242
{
1243 1244 1245 1246 1247
	return	fmt->packing == SOC_MBUS_PACKING_NONE ||
		(fmt->bits_per_sample == 8 &&
		 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
		(fmt->bits_per_sample > 8 &&
		 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
1248 1249 1250 1251 1252
}

static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
				  struct soc_camera_format_xlate *xlate)
{
1253
	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);