- 28 Dec, 2020 22 commits
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Signed-off-by:
Dalton Durst <dalton@ubports.com> -
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When the user has a volume key pressed volume_key variable will contain either value 'down' or 'up', otherwise it will be empty. Signed-off-by:Ondrej Jirman <megous@megous.com>
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Samuel Holland authored
Signed-off-by:Samuel Holland <samuel@sholland.org>
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It turns out that in rare cases, current analytical approach to detect correct DRAM bus width and rank on H6 doesn't work. On some TV boxes with DDR3, incorrect DRAM configuration triggers write leveling error which immediately stops initialization process. Exact reason why this error appears isn't known. However, if correct configuration is used, initalization works without problem. In order to fix this issue, simply try another configuration when any kind of error appears during initialization, not just those related to rank and bus width. Tested-by:
Thomas Graichen <thomas.graichen@googlemail.com> Signed-off-by:
Jernej Skrabec <jernej.skrabec@siol.net>
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So far we did not support the BootROM based FEL USB debug mode on the 64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the SPL runs in AArch64. Returning back to AArch32 was not working as expected, since the RMR reset into 32-bit mode always starts execution in the BootROM, but not in the FEL routine. After some debug and research and with help via IRC, the CPU hotplug mechanism emerged as a solution: If a certain R_CPUCFG register contains some magic, the BootROM will immediately branch to an address stored in some other register. This works well for our purposes. Enable the FEL feature by providing early AArch32 code to first save the FEL state, *before* initially entering AArch64. If we eventually determine that we should return to FEL, we reset back into AArch32, and use the CPU hotplug mechanism to run some small AArch32 code snippet that restores the initially saved FEL state. That allows the normal AArch64 SPL build to be loaded via the sunxi-fel tool, with it returning into FEL mode, so that other payloads can be transferred via FEL as well. Tested on A64, H5 and H6. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Tested-by:
Icenowy Zheng <icenowy@aosc.io>
Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by:
Priit Laes <plaes@plaes.org>
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Switch the SPL boot image generation from using mksunxiboot to the new sunxi_egon format of mkimage. Verified to create identical results for all 152 Allwinner boards. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
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So far we used the separate mksunxiboot tool for generating a bootable image for Allwinner SPLs, probably just for historical reasons. Use the mkimage framework to generate a so called eGON image the Allwinner BROM expects. The new image type is called "sunxi_egon", to differentiate it from the (still to be implemented) secure boot TOC0 image. Signed-off-by: -
To be able to easily share the Allwinner eGON BROM header structure between the tools and the SPL code, move the struct definition into a separate header file. Signed-off-by: -
So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be mostly wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. An almost identical patch (f1239d8aa84d) was merged into the Linux driver and has been backported to stable kernels. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de>
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Previously we have known that R40 has a configuration register for its rank 1, which allows different configuration than rank 0. Reverse engineering of newest libdram of A64 from Allwinner shows that A64 has this register too. It's bit 0 (which enables dual rank in rank 0 configuration register) means a dedicated rank size setup is used for rank 1. Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank DRAM support necessary. Add this support. As we have gained knowledge of asymmetric dual rank, we can now allow R40 dual rank memory setup to work too. Signed-off-by:Icenowy Zheng <icenowy@aosc.io> -
Samuel Holland authored
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Samuel Holland authored
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Samuel Holland authored
Signed-off-by: -
Samuel Holland authored
Signed-off-by: -
Samuel Holland authored
Some platforms, like the Allwinner H6, do not have a separate glue layer around the dwc3. Instead, they rely on the clocks/resets/phys referenced from the dwc3 DT node itself. Add support for enabling the clocks/resets referenced from the dwc3 DT node. Signed-off-by: -
Samuel Holland authored
This driver is needed for XHCI to work on the Allwinner H6 SoC. The driver is copied from Linux v5.7. Signed-off-by: -
Samuel Holland authored
The XHCI controller has its own clock and reset. Add them. Signed-off-by: -
Samuel Holland authored
The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is used, among other things, by the XHCI controller in the H6. To be able to call clk_get_bulk() on the XHCI controller, some device needs to provide all referenced clocks. Since LOSC is a fixed-rate always-on clock, implementation is trivial. Signed-off-by: -
Samuel Holland authored
Import updated device trees from Linux v5.9. Signed-off-by: -
Samuel Holland authored
Import updated device trees from Linux v5.9. Signed-off-by:
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- 22 Dec, 2020 3 commits
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https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini authored
- Update Intel Edison doc information about xFSTK - Move and rename fsp_types.h file to signatures.h
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The fsp_types.h header file contains macros for building signatures of different widths. These signature macros are architecture agnostic, and can be used in all places which use signatures in a data structure. Move and rename the fsp_types.h under the common include header. Signed-off-by:
Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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xFSTK sources got a new home under Edison Firmware Group on GitHub [1]. Update Intel Edison documentation accordingly. While here, fix couple of typos. [1]: https://github.com/edison-fw Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
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- 21 Dec, 2020 2 commits
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Tom Rini authored
Signed-off-by:Tom Rini <trini@konsulko.com>
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Tom Rini authored
Travis-CI is changing their support for FOSS (understandably) to have a limited per-month number of build minutes. Unfortunately for us, the matrix of jobs we run will exhaust that very quickly. Remove the yml file. Thanks for all the builds, Travis-CI! Signed-off-by:
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- 20 Dec, 2020 7 commits
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Since linux commit 2e6cde96873253fd9eb0f20afd8ffd18278cff75 ("arm64: dts: ls1028a: make the eMMC and SD card controllers use fixed indices") mmc0 is the eMMC and mmc1 is the SD card. Also swap it in u-boot to avoid any confusion by the user and to be aligned with linux. Signed-off-by:Michael Walle <michael@walle.cc>
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https://gitlab.denx.de/u-boot/custodians/u-boot-efiTom Rini authored
Pull request for UEFI sub-system for efi-2021-01-rc4 * Provide a tool to create a file with UEFI variables to preseed UEFI variable store. * Make size of UEFI variable store configurable. * Add man pages for commands 'bootefi' and 'button'.
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Heinrich Schuchardt authored
tools/efivar.py allows to prepare a file with UEFI variables to preseed the UEFI variable store. Signed-off-by: -
This script generates EFI variables for U-Boot variable store format. A few examples: - Generating secure boot keys $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_PK/ \ -keyout PK.key -out PK.crt -nodes -days 365 $ efisiglist -a -c PK.crt -o foo.esl $ tools/efivar.py set -i ubootefi.var -n db -d foo.esl -t file $ tools/efivar.py set -i ubootefi.var -n kek -d foo.esl -t file $ tools/efivar.py set -i ubootefi.var -n pk -d foo.esl -t file - Printing out variables $ tools/efivar.py set -i ubootefi.var -n var1 -d foo -t str $ tools/efivar.py set -i ubootefi.var -n var2 -d bar -t str $ tools/efivar.py print -i ubootefi.var var1: 8be4df61-93ca-11d2-aa0d-00e098032b8c EFI_GLOBAL_VARIABLE_GUID NV|BS|RT, DataSize = 0x3 0000000000: 66 6F 6F foo var2: 8be4df61-93ca-11d2-aa0d-00e098032b8c EFI_GLOBAL_VARIABLE_GUID NV|BS|RT, DataSize = 0x3 0000000000: 62 61 72 bar - Removing variables $ tools/efivar.py del -i ubootefi.var -n var1 $ tools/efivar.py set -i ubootefi.var -n var1 -a nv,bs -d foo -t str $ tools/efivar.py print -i ubootefi.var -n var1 var1: 8be4df61-93ca-11d2-aa0d-00e098032b8c EFI_GLOBAL_VARIABLE_GUID NV|BS, DataSize = 0x3 0000000000: 66 6F 6F foo $ tools/efivar.py del -i ubootefi.var -n var1 err: attributes don't match $ tools/efivar.py del -i ubootefi.var -n var1 -a nv,bs $ tools/efivar.py print -i ubootefi.var -n var1 err: variable not found Signed-off-by:Paulo Alcantara (SUSE) <pc@cjr.nz> Correct examples in commit message. Signed-off-by:
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Heinrich Schuchardt authored
Currently the size of the buffer to keep UEFI variables in memory is fixed at 16384 bytes. This size has proven to be too small for some use cases. Make the size of the memory buffer for UEFI variables customizable. Reported-by:
Ilias Apalodimas <ilias.apalodimas@linaro.org>
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Heinrich Schuchardt authored
Provide a description of the bootefi command. Signed-off-by: -
Heinrich Schuchardt authored
Provide a description of the 'button' command. Signed-off-by:
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- 18 Dec, 2020 6 commits
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogicTom Rini authored
- fix Odroid-C4 soft-reboot caused by bad setup of SDCard VDD regulator
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For the proper reboot Odroid-C4 board requires to switch TFLASH_VDD_EN pin to the high impedance mode, otherwise the board is stuck in the middle of loading early stages of the bootloader from SD card. This can be achieved by using the OPEN_DRAIN flag instead if the ACTIVE_HIGH, what will leave the pin in input to achieve high state (pin has the pull-up) and solve the issue. Suggested-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Acked-by:
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Add Micron MT25QL01G flash, used on AST2600 board. Signed-off-by:
Hongwei Zhang <hongweiz@ami.com> Reviewed-by:
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Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by:
Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by:
Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Vignesh R <vigneshr@ti.com>
CC: Tom Rini <trini@konsulko.com>
[jagan: rebase on master]
Signed-off-by: -
This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix Bit. Signed-off-by:
Sean Anderson <seanga2@gmail.com>
Acked-by: Rick Chen <rick@andestech.com> Reviewed-by:
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