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(#755) modify data_src_adc component/worker to match intended design 1 of 1 checklist item completed
- Merged
- 6
- Approved
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Add BRAM to pattern_v2 1 of 1 checklist item completed
- Merged
- 2
- Approved
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Enh/336/cswm to iqstream hdl adapter 1 of 1 checklist item completed
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- 19
- Approved
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Resolve "Rcc work alike of CIC_Decimator" 1 of 1 checklist item completed
- Merged
- 37
- Approved
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Resolve "Asset: fir_real_sse component failing unit test" 1 of 1 checklist item completed
- Merged
- 1
- Approved
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Resolve "CIC_Dec and CIC_Int tests do not run properly" 1 of 1 checklist item completed
- Merged
- Approved
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Merge changes from last av push to github 1 of 1 checklist item completed
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- 16
- Approved
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fixed erroneous printout 1 of 1 checklist item completed
- Merged
- 1
- Approved
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#260 bugfix, also add iqstream_utils.py which is similar to the existing... 1 of 1 checklist item completed
- Merged
- 1
- Approved
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removed erroneous comment 1 of 1 checklist item completed
- Merged
- Approved
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(#221) Changed '/' operator to '//' in call to 'range()' 1 of 1 checklist item completed
- Merged
- Approved
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doc(component): Add HDL worker documentation for data_sink_dac.hdl 1 of 1 checklist item completed
- Merged
- 1
- Approved
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bug(worker): Fix OWD attributes of data_sink_dac on_off port 1 of 1 checklist item completed
- Merged
- 3
- Approved
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Imp/65/framework initialize time service 2 of 2 checklist items completed
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- 42
- Approved
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DAC device worker 2 of 2 checklist items completed
- Merged
- 39
- Approved
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Imp/70/timestamper hdl worker split clocks 1 of 2 checklist items completed
- Merged
- 18
- Approved
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Imp/71/adc worker scdcd 2 of 2 checklist items completed
- Merged
- 84
- Approved
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Feat/61/finalize hts interfaces 3 of 3 checklist items completed
- Merged
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- 16
- Approved
updated