AV-4942: Investigate routing the UART signals which are connected to the PS/MIO to PL/EMIO
Creator: redacted_user_23
Created: 14/Dec/18 1:14 PM
Updated: 10/Jan/19 4:19 PM
Doing some research it seems possible to route some of the signals connected to the zynq's Processing System (PS) multiplexed I/O (MIO) to the Programmable
Logic (PL) extended multiplexed I/O interface (EMIO).
The E310 GPS' UART is connected to the zynq's PS. We want to see if we can route the UART's signals to PL instead so we can use HDL workers.
This guide talks about how to route the signals connected to the PS: http://blog.idv-tech.com/2014/03/22/howto-export-zynq-peripheralsi2c-spi-uart-and-etc-to-pmod-connectors-of-zedboard-using-vivado-2013-4/
Something to note, is that not all peripherals are supported within EMIO. Going through the guide, the GPS' UART, UART1 could be switched to EMIO.
After I switched it to EMIO, UART1 was placed on Bank 13 of the PL/EMIO. The schematic for e310 shows which pins are available. Something to keep in mind when adding the UART1 tx and rx to the constraints file.
Attachments:
e310.pdf