Create Worker Option to specify HDL language (VHD or Verilog)

New feature description

When generating a new worker, a language option to select either VHDL or Verilog is not presented as C++ and C are for creating an RCC worker. By default, only VHDL skeleton files are generated. At most, if HDL selected, C++ and/or C should not be made available to user.

Intended users

HDL Worker developers

Testing requirements

Regression testing according to GUI Test Card should be used to verify.

Define success

VHD option is there and buttons get grayed out

Links/references