W

Wishbone slave generator

Project information

wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:

- Automatically allocated memory layout

- VHDL/Verilog code for the slave module

- C header files for driver development - Nice HTML documentation

Read the wbgen2-Documentation Get the latest version binaries https://gitlab.com/ohwr/attachments/5659/wbgen2-bin.tar.bz2

76 Commits
4 Branches
0 Tags

README
Affero General Public License v1.0

Created on

April 10, 2025

Loading