ODDRX2F, IDDRX1F, IDDR71B and many more do not have a RESET

instances of ODDRX2F (etc) require a ResetSignal:

                for i in range(len(pad)):
                    pad_oddrx2f = Signal()
                    self.specials += Instance("ODDRX2F",
                        i_RST  = ResetSignal("sys"),
                        i_SCLK = ClockSignal("sys"),
                        i_ECLK = ClockSignal("sys2x"),
                        **{f"i_D{n}": getattr(dfi.phases[n//2], dfi_name)[i] for n in range(4)},
                        o_Q    = pad_oddrx2f
                    )

whereas in nmigen/vendor/lattice_ecp5.py that ResetSignal is set to zero:

        def get_oddrx2(sclk, eclk, d0, d1, d2, d3, q):
            for bit in range(len(q)):
                m.submodules += Instance("ODDRX2F",
                    i_SCLK=sclk,
                    i_ECLK=eclk,
                    i_RST=Const(0),
                    i_D0=d0[bit], i_D1=d1[bit], i_D2=d2[bit], i_D3=d3[bit],
                    o_Q=q[bit]
                )

this results in bi-stability at power-on / reset where there is a 50% probability of the DDR IOpad achieving the correct phase, and presumably a 1-in-7 probability of the 7-tap IOpad achieving the correct phase.

further context: https://bugs.libre-soc.org/show_bug.cgi?id=805