Commit 578e609a authored by Alexander Shabarshin's avatar Alexander Shabarshin

fixed generating of ROM for Verilog

parent 42294281
......@@ -2106,7 +2106,7 @@ int main(int argc, char** argv)
fprintf(fo,"input [8:0] addr;\n");
else
fprintf(fo,"input [7:0] addr;\n");
fprintf(fo,"ouput reg [7:0] data;\nalways @(addr) begin\n case(addr)\n");
fprintf(fo,"output reg [7:0] data;\nalways @(addr) begin\n case(addr)\n");
for(uint32_t u=0;u<=ram_last;u++)
{
fprintf(fo," %i : data = 8'h%02X;\n",(ram_start&0xFFFF)+u,ram[u]);
......
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