Commit 42294281 authored by Alexander Shabarshin's avatar Alexander Shabarshin

added generation of ROM for Verilog

parent 149e2ae9
......@@ -2081,6 +2081,40 @@ int main(int argc, char** argv)
fprintf(fo,"\n");
fclose(fo);
}
#if 1
fo = fopen("rom.v","wt");
if(fo!=NULL)
{
fprintf(fo,"module rom(addr,data);\n");
uint32_t romsz = (ram_start&0xFFFF) + ram_last + 1;
printf("codesize with offset: %i\n",romsz);
if(romsz >= 32768)
fprintf(fo,"input [15:0] addr;\n");
else if(romsz >= 16384)
fprintf(fo,"input [14:0] addr;\n");
else if(romsz >= 8192)
fprintf(fo,"input [13:0] addr;\n");
else if(romsz >= 4096)
fprintf(fo,"input [12:0] addr;\n");
else if(romsz >= 2048)
fprintf(fo,"input [11:0] addr;\n");
else if(romsz >= 1024)
fprintf(fo,"input [10:0] addr;\n");
else if(romsz >= 512)
fprintf(fo,"input [9:0] addr;\n");
else if(romsz >= 256)
fprintf(fo,"input [8:0] addr;\n");
else
fprintf(fo,"input [7:0] addr;\n");
fprintf(fo,"ouput reg [7:0] data;\nalways @(addr) begin\n case(addr)\n");
for(uint32_t u=0;u<=ram_last;u++)
{
fprintf(fo," %i : data = 8'h%02X;\n",(ram_start&0xFFFF)+u,ram[u]);
}
fprintf(fo," default: data = 8'h01; // invalid instruction\n endcase\nend\nendmodule\n");
fclose(fo);
}
#endif
#endif
uint64_t ns1 = get_clock();
......
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