Commit abf792e4 authored by Archit Taneja's avatar Archit Taneja Committed by Dr. Git
Browse files

arm64: dts: qcom: msm8996: Add DSI nodes

parent 9a3ed25d
......@@ -548,6 +548,20 @@ ports {
port@0 {
reg = <0>;
mdp5_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
mdp5_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
port@2 {
reg = <2>;
mdp5_intf3_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
......@@ -555,6 +569,162 @@ mdp5_intf3_out: endpoint {
};
};
dsi0: dsi@994000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x994000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 0>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MMSS_MMAGIC_AHB_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_PCLK0_CLK>,
<&mmcc MDSS_ESC0_CLK>;
clock-names = "mdp_core",
"mmagic_iface",
"iface",
"bus",
"core_mmss",
"byte",
"pixel",
"core";
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
<&mmcc PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>,
<&dsi0_phy 1>;
phys = <&dsi0_phy>;
phy-names = "dsi-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi0_phy: dsi-phy@994400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x994400 0x7c>,
<0x994500 0x280>,
<0x994800 0x100>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
<&mmcc MDSS_AHB_CLK>;
clock-names = "mmagic_iface",
"iface";
status = "disabled";
};
dsi1: dsi@996000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x996000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5 0>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MMSS_MMAGIC_AHB_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>,
<&mmcc MDSS_BYTE1_CLK>,
<&mmcc MDSS_PCLK1_CLK>,
<&mmcc MDSS_ESC1_CLK>;
clock-names = "mdp_core",
"mmagic_iface",
"iface",
"bus",
"core_mmss",
"byte",
"pixel",
"core";
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
<&mmcc PCLK1_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>,
<&dsi0_phy 1>;
phys = <&dsi1_phy>;
phy-names = "dsi-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&mdp5_intf2_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
};
};
};
};
dsi1_phy: dsi-phy@996400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x996400 0x7c>,
<0x996500 0x280>,
<0x996800 0x100>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
<&mmcc MDSS_AHB_CLK>;
clock-names = "mmagic_iface",
"iface";
status = "disabled";
};
hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment