Commit 4469628c authored by Ilias Daradimos's avatar Ilias Daradimos

Revert "Merge branch 'GSBC' into 'master'"

This reverts merge request !12
parent 3ec489c7
Pipeline #58469622 passed with stage
in 1 minute and 31 seconds
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
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......
......@@ -707,6 +707,7 @@ typedef struct
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;
/**
* @brief Serial Audio Interface
*/
......@@ -5656,7 +5657,7 @@ typedef struct
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
......@@ -7037,7 +7038,7 @@ typedef struct
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
......@@ -7045,7 +7046,7 @@ typedef struct
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
......@@ -8819,8 +8820,6 @@ typedef struct
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
*/
#define RCC_PLLSAI1_SUPPORT
#define RCC_PLLP_SUPPORT
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
......@@ -14829,7 +14828,6 @@ typedef struct
/******************************************************************************/
/* Aliases for __IRQn */
#define TIM6_IRQn TIM6_DAC_IRQn
#define ADC1_2_IRQn ADC1_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define HASH_RNG_IRQn RNG_IRQn
......@@ -14837,7 +14835,6 @@ typedef struct
#define USB_FS_IRQn USB_IRQn
/* Aliases for __IRQHandler */
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define HASH_RNG_IRQHandler RNG_IRQHandler
......@@ -73,14 +73,11 @@
application
*/
#if !defined (STM32L412xx) && !defined (STM32L422xx) && \
!defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
!defined (STM32L496xx) && !defined (STM32L4A6xx) && \
!defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
/* #define STM32L412xx */ /*!< STM32L412xx Devices */
/* #define STM32L422xx */ /*!< STM32L422xx Devices */
/* #define STM32L431xx */ /*!< STM32L431xx Devices */
/* #define STM32L432xx */ /*!< STM32L432xx Devices */
/* #define STM32L433xx */ /*!< STM32L433xx Devices */
......@@ -120,8 +117,8 @@
* @brief CMSIS Device version number
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
......@@ -136,11 +133,7 @@
* @{
*/
#if defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#if defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
......
......@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
......@@ -444,16 +444,12 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
#if defined(STM32G0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
#if defined(STM32H7)
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#endif
/**
......@@ -498,12 +494,12 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
#else
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
......@@ -544,25 +540,16 @@
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif
#if defined(STM32H7)
#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#endif
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
......@@ -618,7 +605,7 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
......@@ -750,16 +737,6 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
#define I2S_IT_TXE I2S_IT_TXP
#define I2S_IT_RXNE I2S_IT_RXP
#define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP
#define I2S_FLAG_FRE I2S_FLAG_TIFRE
#endif
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
......@@ -884,21 +861,6 @@
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
#if defined(STM32H7)
#define SPI_FLAG_TXE SPI_FLAG_TXP
#define SPI_FLAG_RXNE SPI_FLAG_RXP
#define SPI_IT_TXE SPI_IT_TXP
#define SPI_IT_RXNE SPI_IT_RXP
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
/**
* @}
*/
......@@ -970,10 +932,6 @@
#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
#endif
#if defined(STM32F3)
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif
/**
* @}
*/
......@@ -1330,14 +1288,6 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 */
/**
* @}
*/
......@@ -1820,10 +1770,6 @@
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
* @}
*/
......@@ -2219,6 +2165,19 @@
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
#if defined(STM32WB)
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
#define QSPI_IRQHandler QUADSPI_IRQHandler
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
......@@ -2890,6 +2849,7 @@
#if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
......@@ -3017,7 +2977,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L412xx) || defined (STM32L422xx)
#if defined (STM32G0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
......@@ -3149,7 +3109,6 @@
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
#endif
/**
* @}
......@@ -3339,7 +3298,10 @@
* @{
*/
#define __HAL_LTDC_LAYER LTDC_LAYER
#if defined(STM32F7)
#else
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
#endif
/**
* @}
*/
......
......@@ -35,8 +35,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_H
#define STM32L4xx_HAL_H
#ifndef __STM32L4xx_HAL_H
#define __STM32L4xx_HAL_H
#ifdef __cplusplus
extern "C" {
......@@ -62,7 +62,7 @@
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_BOOT_MAINFLASH 0U
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
......@@ -72,7 +72,7 @@
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
......@@ -188,8 +188,8 @@
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
/**
* @}
......@@ -198,8 +198,8 @@
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
/**
* @}
......@@ -222,7 +222,7 @@
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
......@@ -491,16 +491,16 @@
* @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
*/
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of :
* @param __FASTMODEPLUS__ This parameter can be a value of :
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
......@@ -533,7 +533,7 @@
((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
......@@ -542,7 +542,7 @@
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#endif /* VREFBUF */
#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
......@@ -566,16 +566,6 @@
* @}
*/
/* Exported variables --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
......@@ -674,6 +664,6 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
}
#endif
#endif /* STM32L4xx_HAL_H */
#endif /* __STM32L4xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
......@@ -810,9 +810,7 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
#if defined(CAN2)
#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
#endif
#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
......
......@@ -35,8 +35,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DEF_H
#define STM32L4xx_HAL_DEF_H
#ifndef __STM32L4xx_HAL_DEF
#define __STM32L4xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
......@@ -45,7 +45,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h>
#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
......@@ -208,6 +208,6 @@ typedef enum
}
#endif
#endif /* STM32L4xx_HAL_DEF_H */
#endif /* ___STM32L4xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
......@@ -34,8 +34,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DMA_H
#define STM32L4xx_HAL_DMA_H
#ifndef __STM32L4xx_HAL_DMA_H
#define __STM32L4xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
......@@ -367,9 +367,9 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
/**
* @}
*/
......@@ -377,9 +377,9 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
/**
* @}
*/
......@@ -387,8 +387,8 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_mode DMA mode
* @{
*/
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
/**
* @}
*/
......@@ -396,10 +396,10 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
/**
* @}
*/
......@@ -408,9 +408,9 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
#define DMA_IT_TC DMA_CCR_TCIE
#define DMA_IT_HT DMA_CCR_HTIE
#define DMA_IT_TE DMA_CCR_TEIE
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/**
* @}
*/
......@@ -418,34 +418,34 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
#define DMA_FLAG_GL1 DMA_ISR_GIF1
#define DMA_FLAG_TC1 DMA_ISR_TCIF1
#define DMA_FLAG_HT1 DMA_ISR_HTIF1
#define DMA_FLAG_TE1 DMA_ISR_TEIF1
#define DMA_FLAG_GL2 DMA_ISR_GIF2
#define DMA_FLAG_TC2 DMA_ISR_TCIF2
#define DMA_FLAG_HT2 DMA_ISR_HTIF2
#define DMA_FLAG_TE2 DMA_ISR_TEIF2
#define DMA_FLAG_GL3 DMA_ISR_GIF3
#define DMA_FLAG_TC3 DMA_ISR_TCIF3
#define DMA_FLAG_HT3 DMA_ISR_HTIF3
#define DMA_FLAG_TE3 DMA_ISR_TEIF3
#define DMA_FLAG_GL4 DMA_ISR_GIF4
#define DMA_FLAG_TC4 DMA_ISR_TCIF4
#define DMA_FLAG_HT4 DMA_ISR_HTIF4
#define DMA_FLAG_TE4 DMA_ISR_TEIF4
#define DMA_FLAG_GL5 DMA_ISR_GIF5
#define DMA_FLAG_TC5 DMA_ISR_TCIF5
#define DMA_FLAG_HT5 DMA_ISR_HTIF5
#define DMA_FLAG_TE5 DMA_ISR_TEIF5
#define DMA_FLAG_GL6 DMA_ISR_GIF6
#define DMA_FLAG_TC6 DMA_ISR_TCIF6
#define DMA_FLAG_HT6 DMA_ISR_HTIF6
#define DMA_FLAG_TE6 DMA_ISR_TEIF6
#define DMA_FLAG_GL7 DMA_ISR_GIF7
#define DMA_FLAG_TC7 DMA_ISR_TCIF7
#define DMA_FLAG_HT7 DMA_ISR_HTIF7
#define DMA_FLAG_TE7 DMA_ISR_TEIF7
#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
/**
* @}
*/
......@@ -761,6 +761,6 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
}