I think I might be seeing a similar issue. I'm seeing an DRC error "Copper connection too narrow" but I'm honestly not sure what it's talking about. (See arrow near Pin 1 in image.)
The issue only seems to occur with square pads in my case. Setting pin 1 to even a 1% rounded rectangle pad makes the DRC error go away.
Create project loading in the same footprint I'm using here
Create a zone covering the entire footprint. Set clearance and min. width to 0.2mm. Set pad connections to Solid. Connect the zone to any pin, or no pin at all.
Set project board setup constraints all to zero or very low values. Set Minimum Connection Width to 0.1mm
Run DRC check
I'm running the testing build from today that I believe would already include the previously referenced fix commit, FYI.
Application: KiCad PCB Editor x64 on x64Version: (7.0.0-163-g8f1237e629), release buildLibraries: wxWidgets 3.2.2 FreeType 2.12.1 HarfBuzz 5.0.1 FontConfig 2.14.1 libcurl/7.83.1-DEV Schannel zlib/1.2.13Platform: Windows 10 (build 19043), 64-bit edition, 64 bit, Little endian, wxMSWBuild Info: Date: Mar 5 2023 04:13:37 wxWidgets: 3.2.2 (wchar_t,wx containers) Boost: 1.80.0 OCC: 7.6.2 Curl: 7.83.1-DEV ngspice: 39 Compiler: Visual C++ 1934 without C++ ABIBuild settings: KICAD_SPICE=ON
Turned out that master was using the revised zone fill so it didn't get all the tiny bits of segmented copper. Good test case for DRC, not so great for other things. This fixes the DRC check. Will follow with the zone fill cherry-pick
It looks like the contents of this project are for a different issue
I downloaded the ZIP that I attached, opened the project, performed the DRC on it, zoomed in and I still get the screenshot below with that test case in 7.0.0 .
So IMHO the test case is valid. (I do see that you submitted a fix, so I hope that this applies to my test case as well).
I updated to 7.0.1 - unfortunately the issue persists in my design. I had to update the test case a tiny bit to demontrate this - I shifted a track by 0.2 mm to allow the zonefill to extend a bit further so that it become less wide.
Oh, wow, we have got to do something about our zone fills. Check out what happens to this particular section:
Here, inflating the segmented circle leads to a kind of saw-tooth pattern that is now confusing our algorithm for identifying necks.
I see a solution for this issue in the DRC checker but I think we also need to smooth the output of our inflate routine to both reduce the point count and speed up our display/UI. Fewer triangles = faster responsiveness
Hi @sethhillbrand ,
I recently updated my layout and for some mysterious reason the problem disappeared. So if you would now clone my GitHub repo, you won't be able to reproduce the problem from the latest main branch.
Therefore, I've zipped the "old" project such that you can still reproduce the problem:
@kristofmulier please attach that zip to this issue - drag and drop it into the editor or use the paperclip icon. External links tend to rot and external repos tend to march forward, as we see here. We want the reproducing project archived in the issue tracker so we know we're looking at the same thing and so we can reference it in the future if needed.
Hi,
I'm having this issue too.
What seems to be happening is that there is some kind of "overhang" on the tips of the fill. Like the radius of the "pen" that is used to draw the polygon is big enough to make the sides touch.
Does that make sense?
Sorry I don't have better words to describe it. I hope the picture makes it obvious:
Thanks
Edit: Version info
Application: KiCad PCB Editor x86_64 on x86_64Version: 7.0.10-1.fc39, release buildLibraries: wxWidgets 3.2.4 FreeType 2.13.1 HarfBuzz 8.2.1 FontConfig 2.14.2 libcurl/8.2.1 OpenSSL/3.1.1 zlib/1.2.13 libidn2/2.3.4 nghttp2/1.55.1Platform: Fedora Linux 39 (Workstation Edition), 64 bit, Little endian, wxGTK, gnome-xorg, x11Build Info: Date: Dec 28 2023 00:00:00 wxWidgets: 3.2.4 (wchar_t,wx containers) GTK+ 3.24 Boost: 1.81.0 OCC: 7.6.3 Curl: 8.2.1 ngspice: 41 Compiler: GCC 13.2.1 with C++ ABI 1018Build settings: KICAD_SPICE=ON
Yeah, I tried a bunch of permutations, within reason, of the parameters and can't get it to make the errors disappear. Kinda frustrating because this is not pushing any limits. Just PTH on a 0.1" grid and 0.25mm clearance. Default footprints.
Best I can come up with now is to make all pads round.
If you measure the distance between those two notches, you will find that it is less than the minimum width. The fill does currently generate connections that are too small when the knock outs are spaced just right. We have an open issue to prevent these sorts of small connections but at the moment, the DRC check is reporting correctly
I agree that the DRC check is reporting correctly. However, the bug is in the copper filling algorithm. It fills copper in a way that causes DRC errors.
We have an open issue to prevent these sorts of small connections
That's great KiCAD developers are fixing this. Wonderful. Thank you so much.
@kristofmulier There is now a some testing code to resolve this. You can add ZoneConnectionFiller=1 to your kicad_advanced file to test out the new code in a nightly build. If you do not already have a kicad_advanced file, you can create it in a text editor in %APPDATA%\kicad\8.99