Multiple instances of component from name (lp:#1797038)
Original report created by Samuel Powell (sbear)
Hi all,
I'm a former Cadence Allegro & Virtuoso user, but the university I work at
now doesn't have a license. I have to say I'm rather enjoying how
relatively easy it is to use KiCad so far! I'm currently starting up a
project involving a moderately sized LED array (only ~2500 components :P)
and I find myself missing an aspect of Cadence's schematic capture system
they call "iterated instances" or "bus naming" depending on the context.
In a nutshell, you can name an item (component or wire) in a schematic with
a list of names to replicate that item so many times. E.g. if you set a
component's reference to "U1,U2,U3" it will generate 3 copies of that
component in the netlist, named "U1", "U2", and "U3", respectively. They of
course include some syntax sugar to make the feature more useful: the
pattern "U<start:end>" will expand to "U<start>,...,U<end>".
The semantics of making wire connections to such components are a bit
complicated, but not insurmountable. Let's say you have an iterated
component "U<0:7>" with a pin named "IN", there are 4 cases for how it can
be connected:
1) it's attached to a wire with a singular label -- all of the pins
(U<0>.IN, ..., U<7>.IN) are shorted to that net.
2) it's attached to a wire with a plural label e.g. "A,B,C<3:8>" or
whatever -- the pins are connected to the nets in sequence: U<0>.IN to A,
U<1>.IN to B, U<2>.IN to C<3>, etc...
3) it's attached via an unlabeled wire to the pin of another component with
a single label -- again, all of the pins are shorted to that other
component's pin.
4) it's attached via an unlabeled wire to the pin of another component with
a plural label -- the instance pins are connected in sequence, as with the
labeled wire.
I'm sure there are more details, particularly when it comes to pins with
bus names or hierarchical assemblies, but I hope that was a clear
explanation of the feature. I certainly found it useful when I was working
with Cadence's tools, and with my upcoming project I have some incentive to
devote some time to integrating something like this into KiCad. My current
idea is to implement a limited form using a python script during netlist
export from Eeschema.
I look forward to seeing your thoughts on this!
Cheers,
Sam
P.S. There's a guide from the University of Michigan covering bus naming in
Cadence Virtuoso:
https://www.eecs.umich.edu/courses/eecs427/f10/Common/busnames.pdf
Unfortunately I no longer have access to the official documentation, and I
doubt I would be allowed to share it anyway!
Original tags: eeschema feature.request