Multi-channel parallel components getting swapped between channels

Description

When copying the layout from the source rule zone to the destination rule zones, the order of some components gets mixed up.

V4 of the board from KiCAD 3d viewer image V4 of the board (top) and V2 of the board (Bottom) 20251111_154035 Notice the 2 cap banks and the order of the capacitors between the 3 channels. Specifically, C9/C10/C11 -> C61/C62/C63 -> C36/C37/C38. These have not changed between versions on the schematic and fundamentally haven't changed on the PCB either.

The order of the capacitors seems to be random, and which channel gets the mix-up also seems to be random.

I'll see if I can share the original project or making a minimum viable project.

Steps to reproduce

(Need to verify)

  1. Generate a multi-channel schematic with some identical components in parallel, e.g. multiple capacitors in parallel.
  2. (might be optional) DNP some of the capacitors, but leave some populated.
  3. Do the layout for the first channel.
  4. Run Multi-channel tool
  5. Inspect the order of the capacitors.

KiCad Version

Application: KiCad x64 on x64

Version: 9.0.6, release build

Libraries: wxWidgets 3.2.8 FreeType 2.13.3 HarfBuzz 10.2.0 FontConfig 2.15.0 libcurl/8.13.0-DEV Schannel zlib/1.3.1

Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW

Build Info: Date: Oct 30 2025 19:36:12 wxWidgets: 3.2.8 (wchar_t,wx containers) Boost: 1.88.0 OCC: 7.9.1 Curl: 8.13.0-DEV ngspice: 45.2 Compiler: Visual C++ 1944 without C++ ABI KICAD_IPC_API=ON

Locale: Lang: en_US Enc: UTF-8 Num: 1,234.5 Encoded кΩ丈: D0BACEA9E4B888 (sys), D0BACEA9E4B888 (utf8)