pcbnew: DRC constraint copper-to-hole is broken

Description

When I was writing unit tests, I noticed that the copper-to-hole constraint wasn't working properly. When graphic shapes are assigned to network classes. In addition to these, as a rule, also. See spacing of zones, etc.

However, this is not the case with the copper-to-hole constraint. Here, the element of a net class can pass through the hole without causing an error.

Bildschirmfoto vom 2025-10-09 12-28-21.png

The spacing is set to 1 mm in the net class and the cooper-to-hole constraint. Conductor tracks and zones also have this setting.

test_physical_clearance.zip

Steps to reproduce

  1. Open the layout
  2. Start the DRC

KiCad Version

Application: KiCad PCB Editor x86_64 on x86_64

Version: 9.0.4-1.fc42, release build

Libraries:
	wxWidgets 3.2.8
	FreeType 2.13.3
	HarfBuzz 10.4.0
	FontConfig 2.16.0
	libcurl/8.11.1 OpenSSL/3.2.6 zlib/1.3.1.zlib-ng libidn2/2.3.8 nghttp2/1.64.0

Platform: Fedora Linux 42 (Workstation Edition), 64 bit, Little endian, wxGTK, X11, gnome, x11
OpenGL: NVIDIA Corporation, NVIDIA GeForce RTX 3070/PCIe/SSE2, 4.6.0 NVIDIA 570.169

Build Info:
	Date: Aug 18 2025 00:00:00
	wxWidgets: 3.2.8 (wchar_t,wx containers) GTK+ 3.24
	Boost: 1.83.0
	OCC: 7.8.1
	Curl: 8.11.1
	ngspice: 44.2
	Compiler: GCC 15.2.1 with C++ ABI 1020
	KICAD_IPC_API=ON

Locale: 
	Lang: de_DE
	Enc: UTF-8
	Num: 1.234,5
	Encoded кΩ丈: D0BACEA9E4B888 (sys), D0BACEA9E4B888 (utf8)