Router clearance check fails on pads that have different sizes on each layer

I have create an IC footprint where the bottom layer pads are : 2.5x1.7mm (Oval) Top layer pad : 1.7x1.7mm (oval)

When I drag a trace on the top layer (Yellow arrow) it gives me a clearance violation in the Purple section. However , when I create the trace only partially , (the Orange section) and I copy/paste that trace part (copy / paste orange trace part into the purple section) it doesn't give me the clearance violation (see highlighted track part). Also after copy/pasting (finished track) clearance check passes without any issues.

To me it looks like the real-time clearance check doesn't recognize that the top pad is smaller.

KiCad Version

Application: KiCad x64 on x64

Version: 9.0.0, release build

Libraries:
	wxWidgets 3.2.6
	FreeType 2.13.3
	HarfBuzz 10.2.0
	FontConfig 2.15.0
	libcurl/8.11.1-DEV Schannel zlib/1.3.1

Platform: Windows 11 (build 26120), 64-bit edition, 64 bit, Little endian, wxMSW
OpenGL: Intel, Intel(R) UHD Graphics 630, 4.6.0 - Build 31.0.101.2130

Build Info:
	Date: Feb 19 2025 17:46:53
	wxWidgets: 3.2.6 (wchar_t,wx containers)
	Boost: 1.86.0
	OCC: 7.8.1
	Curl: 8.11.1-DEV
	ngspice: 44
	Compiler: Visual C++ 1942 without C++ ABI
	KICAD_IPC_API=ON

Locale: 
	Lang: en_GB
	Enc: UTF-8
	Num: 1,234.5
	Encoded кΩ丈: D0BACEA9E4B888 (sys), D0BACEA9E4B888 (utf8)