False positive board edge clearance DRC error between arcs on copper and edge cuts layers

Description

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The two arcs share a center, and one has a radius exactly 15 mils larger than the other. The track width is 10 mils. This works out to a clearance of exactly 10 mils between them, but the DRC flags it as too low, claiming it's 9.99996 mils. (which works out to be pretty much spot-on 1 nm less than 10 mils; I assume nanometers are the internal unit.)

Steps to reproduce

  1. Draw an arc on edge.cuts.
  2. Draw a second arc with exactly the same center on any copper layer. Set the second arc's radius slightly higher than the first, and set its thickness such that the clearance between the edge of the second arc and the centerline of the first arc is exactly equal to the board's copper-to-board-edge clearance setting.
  3. Convert the second arc to a track (it may be necessary to assign it a netclass).
  4. Run DRC.

KiCad Version

Application: KiCad PCB Editor x64 on x64

Version: 8.0.5, release build

Libraries:
	wxWidgets 3.2.5
	FreeType 2.13.2
	HarfBuzz 9.0.0
	FontConfig 2.14.2
	libcurl/8.8.0-DEV Schannel zlib/1.3.1

Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW
OpenGL: Intel, Intel(R) UHD Graphics, 4.6.0 - Build 31.0.101.2125

Build Info:
	Date: Sep  7 2024 02:39:48
	wxWidgets: 3.2.5 (wchar_t,wx containers)
	Boost: 1.85.0
	OCC: 7.8.1
	Curl: 8.8.0-DEV
	ngspice: 42
	Compiler: Visual C++ 1939 without C++ ABI

Build settings: