Tracks in positions which offend DRC, pns router and possibly arc approximation (lp:#1833008)
Original report created by eelik (eelik)
I have a tight design with 0402 components and 0.05mm grid. Arc
approximation max err val is 0.001mm. PNS router puts tracks into positions
where they violate DRC. They seem to overlap a bit with the sharp corners
of the clearance outlines which are quite coarse even with the smallest
allowed arc appr max err val. I'm not sure if this can happen when routing
from scratch but I get them when moving the existing tracks with PNS.
Application: Pcbnew
Version: (5.1.0-1008-g945eaceb9), release build
Libraries:
wxWidgets 3.0.4
libcurl/7.61.1 OpenSSL/1.1.1 (WinSSL) zlib/1.2.11 brotli/1.0.6
libidn2/2.0.5 libpsl/0.20.2 (+libidn2/2.0.5) nghttp2/1.34.0
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian,
wxMSW
Build Info:
wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
Boost: 1.68.0
OpenCASCADE Community Edition: 6.9.1
Curl: 7.61.1
Compiler: GCC 8.2.0 with C++ ABI 1013
Build settings:
KICAD_SCRIPTING=ON
KICAD_SCRIPTING_MODULES=ON
KICAD_SCRIPTING_PYTHON3=OFF
KICAD_SCRIPTING_WXPYTHON=ON
KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
KICAD_SCRIPTING_ACTION_MENU=ON
BUILD_GITHUB_PLUGIN=ON
KICAD_USE_OCE=ON
KICAD_USE_OCC=OFF
KICAD_SPICE=ON
Original tags: drc pcbnew pns