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DRC misses edge to copper clearance issue

Description

The attached project demonstrates a DRC issue where in one case the edge to copper clearance of a footprint is caught and another case where the edge to copper clearance of the same footprint is missed. In the screen shot below, the edge to copper clearance (0.254mm) of U19 is clearly violated but it is not flagged by the DRC. However, this clearance violation is flagged for U20. This also affects the head of the master branch. The expectation is that all of the edge to copper clearance errors are correctly identified. I consider this a pretty serious issue but I will wait for confirmation before I set the priority to high.

image

edge-clearance-bug.zip

Steps to reproduce

  1. Open the attached project in KiCad.
  2. Launch the board editor.
  3. Run DRC.
  4. Notice the edge to copper violation error on U19 but not U20.

KiCad Version

Application: KiCad PCB Editor x86_64 on x86_64

Version: 8.0.0-rc2-526-g7e4e80a2e5, debug build

Libraries:
	wxWidgets 3.2.4
	FreeType 2.13.2
	HarfBuzz 8.3.0
	FontConfig 2.14.2
	libcurl/8.5.0 OpenSSL/3.1.4 zlib/1.3 brotli/1.1.0 zstd/1.5.5 libidn2/2.3.7 libpsl/0.21.2 (+libidn2/2.3.4) libssh2/1.11.0 nghttp2/1.58.0 librtmp/2.3 OpenLDAP/2.5.13

Platform: Debian GNU/Linux trixie/sid, 64 bit, Little endian, wxGTK, X11, gnome, x11

Build Info:
	Date: Feb 12 2024 07:26:34
	wxWidgets: 3.2.4 (wchar_t,wx containers) GTK+ 3.24
	Boost: 1.83.0
	OCC: 7.6.3
	Curl: 8.5.0
	ngspice: 41
	Compiler: GCC 13.2.0 with C++ ABI 1018

Build settings:
	KICAD_STDLIB_DEBUG=OFF
	KICAD_STDLIB_LIGHT_DEBUG=OFF
	KICAD_SANITIZE_ADDRESS=OFF
	KICAD_SANITIZE_THREADS=OFF