Export step File with Real Vias
Description
Hi Developers, it is soso great that we have more advanced step file export function. It would be perfect if we have a more realized vias export. As it would be very important for importing into Ansys for simulation.
For instance: This is one screen shot of the exported step file in freecad. This model includes all the tracks, zones and vias as well. The problem is that the vias are just holes on the board.
But in reality, the vias are copper of hollow cylinder. The thickness of the copper wall is 25um for standard process. If would be even better if we can tune the thickness of the vias. As in speical process, the thickness can be increased to around 70um. In Zuken, there is one setting for the via thickness. In the figure below, the board is hidden and I mannually added a real via.
Steps to reproduce
Any pcb with vias and exported would show the problem aforementioned.
KiCad Version
Application: KiCad PCB Editor x64 on x64
Version: 8.0.0-rc1, release build
Libraries: wxWidgets 3.2.4 FreeType 2.12.1 HarfBuzz 8.3.0 FontConfig 2.14.2 libcurl/8.4.0-DEV Schannel zlib/1.3
Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info: Date: Jan 13 2024 16:26:59 wxWidgets: 3.2.4 (wchar_t,wx containers) Boost: 1.83.0 OCC: 7.7.1 Curl: 8.4.0-DEV ngspice: 42 Compiler: Visual C++ 1936 without C++ ABI
Build settings: