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Exporting to Hyperlynx in Pcbnew does not handle microvias correctly

Description

The Hyperlynx file exported by Pcbnew treats all vias (including blind and buried vias) as full stack vias. When the .hyp file is imported to other tools the full-stack vias create inter-layer shorts where the design's buried/blind via is extending into other layers.

Steps to reproduce

Hyperlynx file exports all vias as pad stack type "MDEF" as shown in file excerpt below taken from a .hyp file. But the MDEF pad stack is for full stack vias so when the .hyp file is imported into other tools, any blind/buried/Micro vias are extended onto all layers and cause inter-layer shorts. A defintion of the hyperlynx padstack definition is attached as .png files.

screenshot-1

screenshot-2

{PADSTACK=7, 0.002755906 ("MDEF", 0, 0.007086614, 0.007086614, 0.0, M) }

{NET="ATEST0" (PIN X=3.8779527559 Y=2.3420078740 R="U1.14" P=3)

(PIN X=3.9295275591 Y=2.3415354331 R="U2.4" P=5)

(SEG X1=3.8820866142 Y1=2.3420078740 X2=3.8845861811 Y2=2.3445074409 W=0.0015748031 L="F.Cu")

(SEG X1=3.8845861811 Y1=2.3445074409 X2=3.8937200394 Y2=2.3445074409 W=0.0015748031 L="F.Cu")

(SEG X1=3.8779527559 Y1=2.3420078740 X2=3.8820866142 Y2=2.3420078740 W=0.0015748031 L="F.Cu")

(SEG X1=3.8937200394 Y1=2.3445074409 X2=3.8948818898 Y2=2.3456692913 W=0.0015748031 L="F.Cu")

(VIA X=3.8948818898 Y=2.3456692913 P=7)

(SEG X1=3.9141732283 Y1=2.3456692913 X2=3.8948818898 Y2=2.3456692913 W=0.0015748031 L="In1.Cu")

(VIA X=3.9141732283 Y=2.3456692913 P=7)

(SEG X1=3.9141732283 Y1=2.3456692913 X2=3.9149606299 Y2=2.3464566929 W=0.0015748031 L="In2.Cu")

(SEG X1=3.9149606299 Y1=2.3464566929 X2=3.9220472441 Y2=2.3464566929 W=0.0015748031 L="In2.Cu")

(VIA X=3.9220472441 Y=2.3464566929 P=7) }

  1. Manual fix to .hyp file

In order to handle buried or blind vias or Microvias, layer-to-layer padstacks must be defined as shown below. For completeness each via type consists of a "M"etal pad and an "A"nti-pad pair at the start and finish layers of each via. The Anti-pad may not be entirely necessary if zones are handled correctly

Then all the vias in the file need to be changed to the appropriate pad-stack. This is manageable on small designs but not on large designs. If the exporter could handle this it would be a real boon.

{PADSTACK=7, 0.002755906 ("MDEF", 0, 0.007086614, 0.007086614, 0.0, M) }

{PADSTACK=10, 0.002755906 ("F.Cu", 0, 0.007086614, 0.007086614, 0.0, M) ("F.Cu", 0, 0.010236220, 0.010236220, 0.0, A) ("In1.Cu", 0, 0.007086614, 0.007086614, 0.0, M) ("In1.Cu", 0, 0.010236220, 0.010236220, 0.0, A) }

{PADSTACK=11, 0.002755906 ("In1.Cu", 0, 0.007086614, 0.007086614, 0.0, M) ("In1.Cu", 0, 0.010236220, 0.010236220, 0.0, A) ("In2.Cu", 0, 0.007086614, 0.007086614, 0.0, M) ("In2.Cu", 0, 0.010236220, 0.010236220, 0.0, A) }

{PADSTACK=12, 0.002755906 ("In2.Cu", 0, 0.007086614, 0.007086614, 0.0, M) ("In2.Cu", 0, 0.010236220, 0.010236220, 0.0, A) ("B.Cu", 0, 0.007086614, 0.007086614, 0.0, M) ("B.Cu", 0, 0.010236220, 0.010236220, 0.0, A) }

{NET="ATEST0" (PIN X=3.8779527559 Y=2.3420078740 R="U1.14" P=3)

(PIN X=3.9295275591 Y=2.3415354331 R="U2.4" P=5)

(SEG X1=3.8820866142 Y1=2.3420078740 X2=3.8845861811 Y2=2.3445074409 W=0.0015748031 L="F.Cu")

(SEG X1=3.8845861811 Y1=2.3445074409 X2=3.8937200394 Y2=2.3445074409 W=0.0015748031 L="F.Cu")

(SEG X1=3.8779527559 Y1=2.3420078740 X2=3.8820866142 Y2=2.3420078740 W=0.0015748031 L="F.Cu")

(SEG X1=3.8937200394 Y1=2.3445074409 X2=3.8948818898 Y2=2.3456692913 W=0.0015748031 L="F.Cu")

(VIA X=3.8948818898 Y=2.3456692913 P=10)

(SEG X1=3.9141732283 Y1=2.3456692913 X2=3.8948818898 Y2=2.3456692913 W=0.0015748031 L="In1.Cu")

(VIA X=3.9141732283 Y=2.3456692913 P=11)

(SEG X1=3.9141732283 Y1=2.3456692913 X2=3.9149606299 Y2=2.3464566929 W=0.0015748031 L="In2.Cu")

(SEG X1=3.9149606299 Y1=2.3464566929 X2=3.9220472441 Y2=2.3464566929 W=0.0015748031 L="In2.Cu")

(VIA X=3.9220472441 Y=2.3464566929 P=12) }

KiCad Version

Application: KiCad PCB Editor (64-bit)
Version: (6.0.5), release build
Libraries:
    wxWidgets 3.1.5
    libcurl/7.82.0-DEV Schannel zlib/1.2.12
Platform: Windows 10 (build 19044), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    Date: May 3 2022 00:36:16
    wxWidgets: 3.1.5 (wchar_t,wx containers)
    Boost: 1.79.0
    OCC: 7.6.0
    Curl: 7.82.0-DEV
    ngspice: 36
    Compiler: Visual C++ 1929 without C++ ABI
Build settings:
    KICAD_USE_OCC=ON
    KICAD_SPICE=ON
Edited by William Halliday